ADL5565-EVALZ AD [Analog Devices], ADL5565-EVALZ Datasheet - Page 18

• Manufacturer Part Number: ADL5565-EVALZ
• Description: 6 GHz Ultrahigh Dynamic Range
• Manufacturer: AD [Analog Devices]

ADL5565
INPUT AND OUTPUT INTERFACING
The
differential output driver, as shown in Figure 32. The resistors,
R1 and R2, combined with the ETC1-1-13 balun transformer,
provide a 50 Ω input match for the three input impedances that
change with the variable gain strapping. The input and output
0.1 µF capacitors isolate the VCC/2 bias from the source and
balanced load. The load should equal 200 Ω to provide the
expected ac performance (see the Specifications section and the
Typical Performance Characteristics section).
Table 6. Differential Termination Values for Figure 32
Gain (dB)
6
12
15.5
The differential gain of the
impedance and load, as shown in Figure 33.
The differential gain can be determined using the following
formula. The values of R
in Table 7.
In Equation 1, R
Table 7. Values of R
Gain (dB)
6
12
15.5
NOTES
1. FOR 6dB GAIN (A
2. FOR 12dB GAIN (A
3. FOR 15.5dB GAIN (A
AC
50Ω
AND INPUT B TO BOTH VIN1 AND VIN2.
1
1
ADL5565
/
/
2
2
Figure 32. Differential Input to Differential Output Configuration
A
R
R
V
S
S
=
ETC1-1-13
200
R
0.1µF
0.1µF
G
Figure 33. Differential Input Loading Circuit
can be configured as a differential input to
×
V
G
V
10
R2
R1
= 2), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1.
= 4), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2.
V
is the gain setting resistor (see Figure 1).
R
= 6), CONNECT INPUT A TO BOTH VIP1 AND VIP2
+
0.1µF
0.1µF
L
G
R
VIN1
VIN2
VIP2
VIP1
for Differential Gain
L
G
A
B
for each gain configuration are shown
100Ω
100Ω
R1 (Ω)
29
33
40.2
50Ω
50Ω
ADL5565
VIP2
VIP1
VIN1
VIN2
3V TO 5V
R
100
50
33.5
is dependent on the source
200Ω
200Ω
G
(Ω)
0.1µF
0.1µF
R2 (Ω)
29
33
40.2
5Ω
5Ω
R
R
2
2
L
L
R
L
Rev. | Page 18 of 28
(1)
B
AC
Single-Ended Input to Differential Output
The
to differential output driver, as shown in Figure 34. In this
configuration, the gain of the part is reduced due to the application
of the signal to only one side of the amplifier. The strappable
gain values are listed in Table 8 with the required terminations
to match to a 50 Ω source using R1 and R2. The input and output
0.1 µF capacitors isolate the VCC/2 bias from the source and the
balanced load. The performance for this configuration is shown
in Figure 16 and Figure 21.
Table 8. Single-Ended Termination Values for Figure 34
Gain (dB)
5.3
10.3
13
The single-ended gain configuration of the
on the source impedance and load, as shown in Figure 35.
R
S
Figure 34. Single-Ended Input to Differential Output Configuration
ADL5565
NOTES
1. FOR 5.3dB GAIN (A
2. FOR 10.3dB GAIN (A
3. FOR 13dB GAIN (A
R2
AC
50Ω
AND INPUT B TO VIN1.
AND INPUT B TO VIN2.
VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2.
0.1µF
R1
Figure 35. Single-Ended Input Loading Circuit
R2
+
can also be configured in a single-ended input
0.1µF
0.1µF
R1
VIP2
VIP1
VIN1
VIN2
+
A
B
V
V
0.1µF
V
= 4.5), CONNECT INPUT A TO BOTH
= 1.84), CONNECT INPUT A TO VIP1
= 3.3), CONNECT INPUT A TO VIP2
100Ω
100Ω
50Ω
50Ω
R1 (Ω)
30
30
30
VIP2
VIP1
VIN1
VIN2
3V TO 5V
200Ω
200Ω
ADL5565
0.1µF
0.1µF
5Ω
Data Sheet
5Ω
R2 (Ω)
73
104
154
R
R
2
2
is dependent
L
L
0.1µF
0.1µF
R
R
2
2
L
L