MCP654 MICROCHIP [Microchip Technology], MCP654 Datasheet - Page 27

• Manufacturer Part Number: MCP654
• Description: 50 MHz, 6 mA Op Amps with mCal
• Manufacturer: MICROCHIP [Microchip Technology]

EQUATION 4-7:
The maximum ambient to junction temperature rise
(ΔT
using the maximum expected package power (P
ambient temperature (T
resistance (θ
EQUATION 4-8:
The worst case power de-rating for the op amps in a
particular package can be easily calculated:
EQUATION 4-9:
Several techniques are available to reduce ΔT
given package:
• Reduce θ
• Reduce max(P
4.4
4.4.1
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. See
is the most sensitive to capacitive loads, though all
gains show the same general behavior.
© 2011 Microchip Technology Inc.
Where:
Where:
- Use another package
- Improve the PCB layout (ground plane, etc.)
- Add heat sinks and air flow
- Increase R
- Decrease C
- Limit I
- Decrease V
JA
) and junction temperature (T
n = Number of op amps in package (1 or 2)
T
Jmax
Improving Stability
T
OUT
A
JA
CAPACITIVE LOADS
JA
= Absolute maximum junction
= Ambient temperature (°C)
) found in
Figure
using R
L
DD
L
temperature (°C)
PKG
P
ΔT
T
P
PKG
J
PKG
)
JA
=
2-30. A unity gain buffer (G = +1)
ISO
≤
T
=
A
Table
=
A
T
--------------------------
) and the package thermal
(see
P
Jmax
+
k
∑
PKG
=
n
ΔT
θ
1
JA
1-4:
P
Figure
–
JA
θ
OA
T
JA
J
A
) can be calculated
4-9)
JA
PKG
for a
),
When driving large capacitive loads with these op
amps (e.g., > 20 pF when G = +1), a small series
resistor at the output (R
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-9:
Stabilizes Large Capacitive Loads.
Figure 4-10
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
circuit’s noise gain. For non-inverting gains, G
Signal Gain are equal. For inverting gains, G
1+|Signal Gain| (e.g., -1 V/V gives G
FIGURE 4-10:
for Capacitive Loads.
After selecting R
resulting frequency response peaking and step
response overshoot. Modify R
response is reasonable. Bench evaluation and
simulations with the MCP651/2/4/5/9 SPICE macro
model are helpful.
4.4.2
Figure 4-11
non-inverting amplifiers (V
the input) or inverting amplifiers (V
and V
represent the total capacitance at the input pins; they
include the op amp’s common mode input capacitance
(C
placed in parallel.
CM
100
), board parasitic capacitance and any capacitor
10
M
1.E-11
1
10p
is the input). The capacitances C
R
R
GAIN PEAKING
shows an op amp circuit that represents
G
N
gives recommended R
MCP651/2/4/5/9
Normalized Capacitance; C
ISO
1.E-10
MCP65X
100p
R
for your circuit, double check the
F
Output Resistor, R
Recommended R
G
G
ISO
N
N
= +1
≥ +2
M
in
is a DC voltage and V
Figure
R
ISO
L
C
ISO
/G
1.E-09
L
1n
N
’s value until the
P
), where G
N
DS22146B-page 27
4-9) improves the
L
/G
is a DC voltage
ISO
= +2 V/V).
N
V
(F)
ISO
OUT
ISO
values for
N
N
Values
and C
1.E-08
and the
N
10n
is the
N
P
is
is
G