CLC1200IDP8 CADEKA [Cadeka Microcircuits LLC.], CLC1200IDP8 Datasheet - Page 11

• Manufacturer Part Number: CLC1200IDP8
• Description: Instrumentation Amplifier
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

Data Sheet
Application Information
Basic Operation
The CLC1200 is a monolithic instrumentation amplifier
based on the classic three op amp solution, refer to
the Functional Block Diagram on page 1. The CLC1200
produces a single-ended output reffered to the REF pin
potential.
The internal resistors are trimmed which allows the gain to
be accurately adjusted with one external resistor R
R
preamp stage. As R
transconductance increases to that of the input transistors.
Producing the following advantages:
▪
▪
▪
Gain Selection
The impeadance between pins 1 and 8, R
of the CLC1200. Table 1 shows the required standard
table values of R
1, R
©2008, 2010-2011 CADEKA Microcircuits LLC
G
Open-loop gain increases as the gain is increased,
reducing gain releated errors
Gain-bandwidth increases as the gain is increased,
optimizing frequency response
Reduced input voltage noise which is determined by the
collector current and base resistance of the input devices
1% R
G
49.9k
12.4k
5.49k
2.61k
1.00k
49.9
also
499
249
100
= ∞.
G
(Ω)
G =
determines
Table 1: Recommended R
Caclulated
49.4k
1.990
4.984
9.998
19.93
50.40
100.0
199.4
495.0
991.0
Gain
R G
G
for various calculated gains. For G =
G
is reduced for larger gains, the
+ 1;
the
0.1% R
transconductance
49.3k
12.4k
5.49k
2.61k
1.01k
98.8
49.3
R G =
499
249
G
(Ω)
G
Values
49.4k
G - 1
G
, sets the gain
Calculated
1,003.0
2.002
4.984
9.998
19.93
49.91
100.0
199.4
501.0
Gain
G
of
.
the
Follow these guidelines for improved performance:
▪
▪
▪
Common Mode Rejection
The CLC1200 offers high CMRR. To acheive optimal CMRR
performance:
▪
▪
In many applications, shielded cables are used to
minimize noise. Properly drive the shield for best CMRR
performance over frequency. Figures 1 and 2 show active
data guards that are configured to improve AC common-
mode rejections. the capacitances of input cable shields
are “bootstrapped” to minimize the capacitance mismatch
between the inputs.
To maintain gain accuracy, use 0.1% to 1% resistors
To minimize gain error, avoid high parasitic resistance in
series with R
To minimize gain drift, use low TC resistors (<10ppm/°C)
Connect the reference terminal (pin 5) to a low
impedance source
Minimize capacitive and resistive differences between
the inputs
Figure 1: Common-mode Shield Driver
100
100
Figure 2: Differential Shield Driver
100
G
+
+
CLCxxx
-
-
_
+
+ Input
- Input
+ Input
- Input
-V S
R G
R G / 2
R G / 2
_
+
CLC1200
www.cadeka.com
-V S
_
+
+V S
CLC1200
-V S
+V S
REF
REF
Output
Output
11