CLC446A8B NSC [National Semiconductor], CLC446A8B Datasheet - Page 5

• Manufacturer Part Number: CLC446A8B
• Description: 400MHz, 50mW Current-Feedback Op Amp
• Manufacturer: NSC [National Semiconductor]

DC Gain (unity gain buffer)
The recommended R
is left open. Parasitic capacitance at the inverting node
may require a slight increase of R
frequency response.
DC Gain (inverting)
The inverting DC voltage gain for the configuration
shown in Figure 2 is
The normalized gain plots in the Typical Performance
Characteristics section show different feedback
resistors (R
recommended for obtaining the highest bandwidth with
minimal peaking. The resistor R
non-inverting input.
For |A
ues to calculate the recommended value of R
≥ 5, the minimum recommended R
Select R
gains, R
This can be solved by driving R
buffer like the CLC111, or increasing R
See the AC Design (small signal bandwidth)
sub-section for the tradeoffs.
DC gain accuracy is usually limited by the tolerance of R
and R
DC Gain (transimpedance)
Figure 3 shows a transimpedance circuit where the cur-
rent I
source’s output resistance is much greater than R
The DC transimpedance gain is:
The recommended R
the inverting node may require a slight increase of R
maintain a flat frequency response.
DC gain accuracy is usually limited by the tolerance of R
in
v
g
| < 5, use linear interpolation on the nearest A
.
g
is injected at the inverting node. The current
g
becomes small and will load the previous stage.
V
in
to set the DC gain:
f
) for different gains. These values of R
Figure 2: Inverting Gain
R
t
f
A
f
3
2
for unity gain buffers is 453 . R
is 453 . Parasitic capacitance at
v
-
+
CLC446
V
V
CC
EE
7
4
R
R
g
f
6.8 F
0.1 F
0.1 F
6.8 F
+
t
.
R
g
provides DC bias for the
f
6
+
with a low impedance
f
R
A
is 200 .
g
R
f
to maintain a flat
V
R
A
I
in
o
v
f
.
V
f
o
f
. For |A
R
and R
At large
f
f
.
v
f
val-
are
f
f
to
g
v
.
g
|
.
f
5
DC Design (level shifting)
Figure 4 shows a DC level shifting circuit for inverting
gain configurations. V
shift of
output produced by V
DC Design (single supply)
Figure 5 is a typical single-supply circuit. R
a voltage divider that sets the non-inverting input DC volt-
age. This circuit has a DC gain of 1. A low
frequency zero is set by R
itor
previous stage. Both capacitors make a high pass
response; high frequency gain is determined by R
The complete gain equation for the circuit in Figure 5 is:
C
1
I
in
V
isolates
V
Figure 3: Transimpedance Gain
ref
Figure 4: Level Shifting Circuit
Figure 5: Single Supply Circuit
V
V
in
V
ref
V
in
in
o
R
R
R
t
ref
C
f
1
1 s
s
R
3
2
R
, which is independent of the DC
R
its
in
t
V
1
2
1
.
ref
CLC446
+
-
CC
1
V
V
CC
EE
7
1 s
4
DC
g
produces a DC output level
+
CLC446
-
R
and C
C
g
6.8 F
0.1 F
0.1 F
6.8 F
2
+
R
CLC446
1 s
+
-
2
6
f
bias
+
V
2
R
CC
1
. The coupling capac-
f
2
R
R
R
point
g
f
f
http://www.national.com
1
V
V
and R
o
o
from
f
V
and R
o
2
form
the
g
.