74AUP3G04DC NXP [NXP Semiconductors], 74AUP3G04DC Datasheet

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74AUP3G04DC

Manufacturer Part Number
74AUP3G04DC
Description
Low-power triple inverter
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.74AUP3G04DC.pdf (17 pages)
1. General description
2. Features
The 74AUP3G04 provides a low-power, low-voltage triple inverting buffer.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial Power-down applications using I
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
I
I
I
I
I
I
I
I
I
I
I
CC
74AUP3G04
Low-power triple inverter
Rev. 03 — 8 October 2009
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78B Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
N
N
N
N
N
N
N
N
range from 0.8 V to 3.6 V.
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101D exceeds 1000 V
circuitry provides partial Power-down mode operation
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 A (maximum)
CC
Product data sheet
OFF
. The I
OFF

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74AUP3G04DC Summary of contents

Page 1

Low-power triple inverter Rev. 03 — 8 October 2009 1. General description The 74AUP3G04 provides a low-power, low-voltage triple inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times across ...

Page 2

... C to +125 C 74AUP3G04GT +125 C 74AUP3G04GD +125 C 74AUP3G04GM +125 C 4. Marking Table 2. Marking codes Type number 74AUP3G04DC 74AUP3G04GT 74AUP3G04GD 74AUP3G04GM [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram ...

Page 3

NXP Semiconductors 6. Pinning information 6.1 Pinning 74AUP3G04 GND 4 001aag450 Fig 4. Pin configuration SOT765-1 (VSSOP8) 74AUP3G04 GND 4 Transparent top view Fig 6. Pin configuration SOT996-2 ...

Page 4

NXP Semiconductors 7. Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System ...

Page 5

NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter amb V HIGH-level input voltage IH V LOW-level input voltage IL V ...

Page 6

NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter +85 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V ...

Page 7

NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter +125 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V ...

Page 8

NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay nA to nY; see ...

Page 9

NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions pF and power dissipation ...

Page 10

NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance Z T ...

Page 11

NXP Semiconductors 13. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions ...

Page 12

NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A ...

Page 13

NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT A ...

Page 14

NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 ...

Page 15

NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 12. Revision history Document ID Release date 74AUP3G04_3 20091008 ...

Page 16

NXP Semiconductors 16. Legal information 16.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 17

NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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