V62C2161024L-100T MOSEL [Mosel Vitelic, Corp], V62C2161024L-100T Datasheet - Page 5

• Manufacturer Part Number: V62C2161024L-100T
• Description: Ultra Low Power 64K x 16 CMOS SRAM
• Manufacturer: MOSEL [Mosel Vitelic, Corp]

REV. 1.1 April 2001 V62C2161024L(L)
Notes (Read Cycle)
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3.
4. At any given temperature and voltage condition
5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
6. Device is continuously selected with CE = V
7. Address valid prior to coincident with CE transition Low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
9. For test conditions, see AC Test Condition, Figure A.
Timing Waveform of Read Cycle 1 (Address Controlled)
Timing Waveform of Read Cycle 2
device.
cycle.
t
HZ
Data Out
CE
OE
Address
(BLE/BHE)
Data Out
Address
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit condition referenced to V
Previous Data Valid
High-Z
t
OH
t
t
BLZ(4,5)
LZ(4,5)
IL
t
t
t
AA
BA
OLZ
t
.
OE
t
t
HZ
ACE
(max.) is less than
t
AA
t
RC
t
RC
5
Data Valid
t
LZ
Data Valid
(min.) both for a given device and from device to
t
t
BHZ(3,4,5)
HZ(3,4,5)
t
OHZ
t
OH
V62C2161024L(L)
OH
or V
OL
levels.