AT93C46A-10TC-2.5 ATMEL [ATMEL Corporation], AT93C46A-10TC-2.5 Datasheet

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AT93C46A-10TC-2.5

Manufacturer Part Number
AT93C46A-10TC-2.5
Description
3-Wire Serial EEPROM 1K (64 x 16)
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Features
Description
The AT93C46A provides 1024 bits of serial electrically-erasable programmable read-
only memory (EEPROM) organized as 64 words of 16 bits each. The device is opti-
mized for use in many industrial and commercial applications where low-power and
low-voltage operation are essential. The AT93C46A is available in space-saving 8-
lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages.
The AT93C46A is enabled through the Chip Select pin (CS) and accessed via a three-
wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a Read instruction at DI, the address is decoded and the data is
clocked out serially on the data output DO pin. The write cycle is completely self-timed
and no separate erase cycle is required before write. The write cycle is only enabled
when the part is in the erase/write enable state. When CS is brought high following the
initiation of a write cycle, the DO pin outputs the ready/busy status of the part.
The AT93C46A is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Table 1. Pin Configuration
Pin Name
CS
SK
DI
DO
GND
VCC
Low-voltage and Standard-voltage Operation
Three-wire Serial Interface
2 MHz Clock Rate (5V) Compatibility
Self-timed Write Cycle (10 ms max)
High Reliability
Automotive Grade, Extended Temperature, and Lead-free/Halogen-free Devices
Available
8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
– 2.7 (V
– 1.8 (V
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
CC
CC
= 2.7V to 5.5V)
= 1.8V to 5.5V)
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
DO
CS
SK
DO
DI
CS
SK
DI
DO
CS
SK
DI
8-lead TSSOP
1
2
3
4
8-lead PDIP
1
2
3
4
1
2
3
4
8-lead SOIC
8
7
6
5
8
7
6
5
8
7
6
5
VCC
DC
NC
GND
VCC
DC
NC
GND
VCC
DC
NC
GND
Three-wire
Serial EEPROM
1K (64 x 16)
AT93C46A
Note:
Not recommended for new
design; please refer to
AT93C46E datasheet.
Rev. 0539K–SEEPR–2/07
1

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AT93C46A-10TC-2.5 Summary of contents

Page 1

... The AT93C46A is available in space-saving 8- lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages. The AT93C46A is enabled through the Chip Select pin (CS) and accessed via a three- wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output DO pin ...

Page 2

... Absolute Maximum Ratings* Operating Temperature......................................−55°C to +125°C Storage Temperature .........................................−65°C to +150°C Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA AT93C46A 2 *NOTICE: Figure 1. Block Diagram MEMORY ARRAY REGISTER DECODE GENERATOR Stresses beyond those listed under “Absolute Maximum Ratings” ...

Page 3

Table 2. Pin Capacitance Applicable over recommended operating range from T Symbol Test Conditions C Output Capacitance (DO) OUT C Input Capacitance (CS, SK, DI) IN Note: This parameter is characterized and is not 100% tested. Table 3. DC ...

Page 4

... Output Delay to “0” PD0 Status Valid High t DF Impedance t Write Cycle Time WP (1) Endurance 5.0V, 25°C Note: 1. This parameter is characterized and is not 100% tested. AT93C46A 4 = −40° 85° Test Condition 4.5V ≤ V ≤ 5.5V CC 2.7V ≤ V ≤ 5.5V CC 1.8V ≤ V ≤ 5.5V CC 4.5V ≤ V ≤ 5.5V CC 2.7V ≤ ...

Page 5

... The AT93C46A is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host pro- cessor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the appropriate op code and the desired memory address location. ...

Page 6

... The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. µ s (1) Table 6. Organization Key for Timing Diagrams I 5.0V ± 10%. CC AT93C46A 0539K–SEEPR–2/ ...

Page 7

Figure 3. READ Timing High Impedance 1 Figure 4. EWEN Timing Note: 1. Requires a minimum of nine clock cycles. 1 Figure 5. EWDS Timing Note: 1. Requires a minimum ...

Page 8

... HIGH IMPEDANCE DO (1 ),( 2 ) Figure 7. WRAL Timing HIGH IMPEDANCE DO Notes: 1. Valid only 4.5V to 5.5V Requires a minimum of nine clock cycles. Figure 8. ERASE Timing HIGH IMPEDANCE DO AT93C46A 8 ... ... ... A0 A ... N-1 N BUSY READY ...

Page 9

Figure 9. ERAL Timing HIGH IMPEDANCE DO Note: 1. Valid only 4.5V to 5.5V. CC 0539K–SEEPR–2/ STANDBY CHECK STATUS BUSY HIGH IMPEDANCE ...

Page 10

... AT93C46A-10PU-2.7 AT93C46A-10PU-1.8 AT93C46A-10SU-2.7 AT93C46A-10SU-1.8 AT93C46A-10TU-2.7 AT93C46A-10TU-1.8 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in Table 3 on page 3 and Table 4 on page 4. Not recommended for new design. Please see AT93C46E datasheet. 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" ...

Page 11

Packaging Information 8P3 – PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured ...

Page 12

... JEDEC SOIC Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT93C46A TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing ...

Page 13

TSSOP Pin 1 indicator this corner N Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, ...

Page 14

... Revision History AT93C46A 14 Doc. Rev. Date Comments 0539K 2/2007 Implemented revision history. Added Note to page 1 and ordering information; Not recommended for new design; please refer to AT93C46E datasheet. 0539K–SEEPR–2/07 ...

Page 15

... Atmel Corporation. All rights reserved. Atmel trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 ...

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