AT93C56A-W1.8-11 ATMEL [ATMEL Corporation], AT93C56A-W1.8-11 Datasheet - Page 5

• Manufacturer Part Number: AT93C56A-W1.8-11
• Description: Three-wire Serial EEPROM
• Manufacturer: ATMEL [ATMEL Corporation]

Table 5. Instruction Set for the AT93C56A and AT93C66A
Note:
Functional Description
3378K–SEEPR–12/06
Instruction
READ
EWEN
ERASE
WRITE
ERAL
WRAL
EWDS
The X’s in the address field represent don’t care values and must be clocked.
SB
1
1
1
1
1
1
1
Code
Op
10
00
11
01
00
00
00
10XXXXXXX
01XXXXXXX
00XXXXXXX
11XXXXXXX
The AT93C56A/66A is accessed via a simple and versatile three-wire serial communi-
cation interface. Device operation is controlled by seven instructions issued by the host
processor. A valid instruction starts with a rising edge of CS and consists of a Start
Bit (logic “1”) followed by the appropriate Op Code and the desired memory address
location.
READ (READ): The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C56A/66A
supports sequential read operations. The device will automatically increment the inter-
nal address pointer and clock out the next memory location as long as Chip Select (CS)
is held high. In this case, the dummy bit (logic “0”) will not be clocked out between mem-
ory locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled
until an EWDS instruction is executed or V
ERASE (ERASE): The Erase instruction programs all bits in the specified memory loca-
tion to the logical “1” state. The self-timed erase cycle starts once the ERASE instruction
and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is
brought high after being kept low for a minimum of 250 ns (t
indicates that the selected memory location has been erased, and the part is ready for
another instruction.
A
A
A
8
8
8
x 8
– A
– A
– A
0
0
0
Address
10XXXXXX
01XXXXXX
00XXXXXX
11XXXXXX
A
A
A
x 16
7
7
7
– A
– A
– A
0
0
0
D
D
7
7
x 8
– D
– D
0
0
Data
D
D
15
15
x 16
CC
– D
– D
power is removed from the part.
0
0
Comments
Reads data stored in memory, at
specified address.
Write enable must precede all
programming modes.
Erases memory location A
Writes memory location A
Erases all memory locations. Valid
only at V
Writes all memory locations. Valid
only at V
Register cleared.
Disables all programming
instructions.
CC
CC
CS
= 4.5V to 5.5V.
= 5.0V ±10% and Disable
). A logic “1” at pin DO
n
n
– A
– A
0
0
.
.
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