24LCS21A-/P MICROCHIP [Microchip Technology], 24LCS21A-/P Datasheet - Page 6

• Manufacturer Part Number: 24LCS21A-/P
• Manufacturer: MICROCHIP [Microchip Technology]

24LCS21A
FIGURE 3-3:
DS21161G-page 6
Note 1: The base flowchart is copyright © 1993, 1994, 1995 Video Electronic Standard Association (VESA) from
DDC™ Circuit Powered
2: The dash box and text “The 24LCS21A and... inside dash box.” are added by Microchip Technology Inc.
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LCS21A.
Display Power-on
from +5 volts
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
or
No
No
No
DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA
No
Send EDID™ continuously
using Vsync as clock
Switch to DDC2™ mode.
Reset Vsync counter = 0
Increment VCLK counter
Set Vsync counter = 0
Stop sending EDID.
Switch back to DDC1™
Communication
transition on SCL
Counter = 128 or
or start timer
transition state
(if appropriate)
DDC2 address
transition on
timer expired?
High-to-low
SCL, SDA or
Display has
VCLK lines?
Yes
Change on
High - low
present?
Is Vsync
received?
optional
is idle
SCL?
mode.
VCLK
cycle?
Valid
?
?
Yes
Yes
Yes
Yes
No
Yes
Yes
No
No
No
Yes
Reset counter or timer
The 24LCS21A was designed to
comply to the portion of flowchart inside dash box
specification to determine
idle. Display waiting for
DDC2 communication
See Access.bus
correct procedure.
Valid Access.bus
address byte.
Access.bus
transition on
High-to-low
received?
Is display
capable?
address
address?
DDC2B
SCL?
Yes
Yes
Yes
No
TM
No
No
© 2005 Microchip Technology Inc.
Yes
No
Respond to DDC2B
Receive DDC2B
command
command
®