24LCS21A-/P MICROCHIP [Microchip Technology], 24LCS21A-/P Datasheet - Page 8

• Manufacturer Part Number: 24LCS21A-/P
• Manufacturer: MICROCHIP [Microchip Technology]

24LCS21A
FIGURE 3-5:
FIGURE 3-6:
3.1.6
After generating a Start condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010000) for the 24LCS21A.
The eighth bit of slave address determines whether the
master device wants to read or write to the 24LCS21A
(Figure 3-7).
The 24LCS21A monitors the bus for its corresponding
slave
Acknowledge bit if the slave address was true and it is
not in a programming mode.
DS21161G-page 8
Operation
SDA
IN
SDA
OUT
SCL
SDA
SCL
Read
Write
T
SU
address
:
STA
T
SU
SLAVE ADDRESS
:
STA
T
SP
continuously.
Slave Address
T
BUS TIMING START/STOP
BUS TIMING DATA
Start
AA
1010000
1010000
T
F
T
HD
T
:
STA
T
LOW
It
HD
:
STA
generates
T
T
HIGH
HD
R/W
:
DAT
1
0
an
T
AA
FIGURE 3-7:
V
HYS
T
1
SU
:
Start
DAT
0
T
T
SU
SU
:
STO
:
STO
1
Slave Address
CONTROL BYTE
ALLOCATION
© 2005 Microchip Technology Inc.
T
0
R
Stop
0
Read/Write
T
BUF
0
R/W
0
A