AT25010A-10PE-2.7 ATMEL [ATMEL Corporation], AT25010A-10PE-2.7 Datasheet - Page 7
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AT25010A-10PE-2.7
Manufacturer Part Number
AT25010A-10PE-2.7
Description
SPI Serial Extended TEMPERATURE EEPROMS 1K 2K 4K
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT25010A-10PE-2.7.pdf
(18 pages)
Functional
Description
5087B–SEEPR–1/05
The AT25010A/020A/040A is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25010A/020A/040A utilizes an 8-bit instruction register. The list of instructions
and their operation codes are contained in Table 5. All instructions, addresses, and data
are transferred with the MSB first and start with a high-to-low CS transition.
Table 5. Instruction Set for the AT25010A/020A/040A
Note:
WRITE ENABLE (WREN): The device will power up in the write disable state when V
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction. The WP pin must be held high during a WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is indepen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the block write protection bits
indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6. Status Register Format
Table 7. Read Status Register Bit Definition
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25010A/020A/040A is divided into four array seg-
ments. One-quarter, one-half, or all of the memory segments can be protected. Any of
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4 − 6 are “0”s when device is not in an internal write cycle.
Bits 0 − 7 are “1”s during an internal write cycle.
Bit 7
X
“A” represents MSB address bit A8.
Bit 6
X
Definition
Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the write
cycle is in progress.
Bit 1= “0” indicates the device is not write-enabled. Bit 1 = “1” indicates the
device is write-enabled.
See Table 8 on page 8.
See Table 8 on page 8.
Instruction Format
0000 X110
0000 X100
0000 X101
0000 X001
0000 A011
0000 A010
Bit 5
X
Bit 4
X
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Bit 3
AT25010A/020A/040A
BP1
Bit 2
BP0
WEN
Bit 1
Bit 0
RDY
CC
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