AT88SC1616C-WI ATMEL [ATMEL Corporation], AT88SC1616C-WI Datasheet - Page 6

• Manufacturer Part Number: AT88SC1616C-WI
• Description: CryptoMemory 16 Kbit
• Manufacturer: ATMEL [ATMEL Corporation]

Device Operation For
Synchronous
Protocols
Figure 3. Bus Timing for 2 wire communications
Figure 4. Write Cycle Timing:
6
SCL: Serial Clock, SDA: Serial Data I/O
SCL: Serial Clock, SDA: Serial Data I/O
AT88SC1616C
SDA
SCL
WORDn
8th BIT
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 5 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 6 on page 7).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 6 on page 7).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
Note:
The write cycle time t
end of the internal clear/write cycle.
ACK
CONDITION
STOP
WR
is the time from a valid stop condition of a write sequence to the
t
WR
(1)
CONDITION
START
2030IS–SMIC–04/07