IS42S16800B ISSI [Integrated Silicon Solution, Inc], IS42S16800B Datasheet - Page 49

• Manufacturer Part Number: IS42S16800B
• Description: 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
• Manufacturer: ISSI [Integrated Silicon Solution, Inc]

WRITE With Auto Precharge interrupted by a WRITE
IS42S81600B,
WRITE With Auto Precharge interrupted by a READ
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. E
05/01/06
A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing (CAS latency) later.
The PRECHARGE to bank n will begin after t
where t
The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m.
Internal States
Internal States
COMMAND
COMMAND
ADDRESS
ADDRESS
DPL
BANK m
BANK m
BANK n
BANK n
begins when the READ to bank m is registered.
CLK
CLK
DQ
DQ
Page Active
Page Active
T0
T0
NOP
NOP
IS42S16800B
WRITE - AP
WRITE - AP
BANK n,
BANK n,
BANK n
BANK n
T1
T1
COL a
COL a
D
D
Page Active
IN
IN
WRITE with Burst of 4
a
a
Page Active
WRITE with Burst of 4
T2
D
T2
D
NOP
NOP
DPL
IN
IN
a+1
a+1
is met,
READ - AP
BANK m,
BANK m
T3
T3
D
NOP
1-800-379-4774
COL b
IN
Interrupt Burst, Write-Back
a+2
4. Interrupted by a WRITE (with or without auto precharge):
t
CAS Latency - 3 (BANK m)
DPL
AWRITE to bank m will interrupt a WRITE on bank n when
registered. The PRECHARGE to bank n will begin after
t
is registered. The last valid data WRITE to bank n will be
data registered one clock prior to a WRITE to bank m.
DPL
- BANK n
WRITE - AP
BANK m,
BANK m
T4
T4
NOP
COL b
D
is met, where t
Interrupt Burst, Write-Back
IN
READ with Burst of 4
b
t
DPL
WRITE with Burst of 4
- BANK n
T5
T5
D
NOP
NOP
IN
b+1
DPL
begins when the WRITE to bank m
T6
T6
D
NOP
NOP
IN
D
Precharge
t
OUT
b+2
RP - BANK n
b
t
Precharge
RP - BANK n
DON'T CARE
DON'T CARE
T7
T7
D
NOP
D
NOP
Write-Back
IN
Precharge
OUT
ISSI
b+3
t
t
RP - BANK m
DPL - BANK m
b+1
49
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