M95010-BN3 STMICROELECTRONICS [STMicroelectronics], M95010-BN3 Datasheet - Page 16

• Manufacturer Part Number: M95010-BN3
• Description: 4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M95040, M95020, M95010
Read from Memory Array (READ)
As shown in
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and address byte are
then shifted in, on Serial Data Input (D). For the
M95040, the most significant address bit, A8, is in-
corporated as bit b3 of the instruction byte, as
shown in
internal address register, and the byte of data at
that address is shifted out, on Serial Data Output
(Q).
If Chip Select (S) continues to be driven Low, an
internal bit-pointer is automatically incremented at
each clock cycle, and the corresponding data bit is
shifted out.
When the highest address is reached, the address
counter rolls over to zero, allowing the Read cycle
Figure 12. Read from Memory Array (READ) Sequence
Note: Depending on the memory size, as shown in
16/37
S
C
D
Q
Table
Figure
5.. The address is loaded into an
12., to send this instruction to
0
1
High Impedance
2
Instruction
3
A8
4
5
Table
6
7
6., the most significant address bits are Don’t Care.
A7
8
A6 A5 A4 A3 A2 A1 A0
9 10 11 12 13 14 15 16 17 18 19
Byte Address
to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruc-
tion.
The Read cycle is terminated by driving Chip Se-
lect (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not execut-
ed, if a Write cycle is currently in progress.
Table 6. Address Range Bits
Address Bits
Device
7
M95040
6
A8-A0
5
Data Out
4
3
20 21 22
2
M95020
A7-A0
1
0
AI01440E
M95010
A6-A0