M95010-R STMICROELECTRONICS [STMicroelectronics], M95010-R Datasheet - Page 22

• Manufacturer Part Number: M95010-R
• Description: 4 Kbit, 2 Kbit and 1 Kbit Serial SPI bus EEPROM with high speed Clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Instructions
6.6
22/42
Write to Memory Array (WRITE)
As shown in
Low. The bits of the instruction byte, address byte, and at least one data byte are then
shifted in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) High after the rising edge of Serial
Clock (C) that latches the last data bit, and before the next rising edge of Serial Clock (C)
occurs anywhere on the bus. In the case of
data byte has been latched in, indicating that the instruction is being used to write a single
byte. The self-timed Write cycle starts, and continues for a period t
Table 18
If, though, Chip Select (S) continues to be driven Low, as shown in
of input data is shifted in. In this way, all the bytes from the given address to the end of the
same page can be programmed in a single instruction.
If Chip Select (S) still continues to be driven Low, the next byte of input data is shifted in, and
is used to overwrite the byte at the start of the current page.
The instruction is not accepted, and is not executed, under the following conditions:
Figure 12. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in
S
C
D
Q
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
if a Write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven High, at a byte
boundary (after the rising edge of Serial Clock (C) that latches the last data bit, and
before the next rising edge of Serial Clock (C) occurs anywhere on the bus)
if Write Protect (W) is Low or if the addressed page is in the region protected by the
Block Protect (BP1 and BP0) bits.
to
Table
Figure
0
1
High Impedance
22), at the end of which the Write in Progress (WIP) bit is reset to 0.
2
12, to send this instruction to the device, Chip Select (S) is first driven
Instruction
3
A8
4
5
6
7
A7
8
A6 A5 A4 A3 A2 A1 A0
9 10 11 12 13 14 15 16 17 18 19
Table
Byte Address
Figure
6, the most significant address bits are Don’t Care.
12, this occurs after the eighth bit of the
7
6
M95040, M95020, M95010
5
Data Byte
WC
Figure
4
(as specified in
3
20 21 22 23
2
13, the next byte
1
0
AI01442D