M24256-BRDW6G STMICROELECTRONICS [STMicroelectronics], M24256-BRDW6G Datasheet
M24256-BRDW6G
Related parts for M24256-BRDW6G
M24256-BRDW6G Summary of contents
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... Enhanced ESD/Latch-Up Protection More than 1,000,000 Write cycles More than 40-year data retention Packages – ECOPACK® (RoHS compliant) October 2006 M24512-W M24512-R M24256-BW M24256-BR 512 Kbit and 256 Kbit Serial I²C bus EEPROM with three Chip Enable lines Rev SO8 (MW) ...
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... ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . . . 15 3.10 Minimizing System Delays by Polling On ACK . . . . . . . . . . . . . . . . . . . . . 16 3.11 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.12 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.13 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.14 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.15 Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/31 M24512-W, M24512-R, M24256-BW, M24256- Operating supply voltage Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ...
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... M24512-W, M24512-R, M24256-BW, M24256- and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Contents 3/31 ...
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... SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . 26 Table 17. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 27 Table 18. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4/31 M24512-W, M24512-R, M24256-BW, M24256-BR Table 7 and Table Table 8 and Table ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Maximum R Value versus Bus Parasitic Capacitance (C) for Figure Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6. Write mode sequences with (data write inhibited Figure 7 ...
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... Summary description 1 Summary description The M24512-W, M24512-R, M24256-BW and M24256-BR devices are I electrically erasable programmable memories (EEPROM). They are organized × 8 bits and 32 Kb × 8 bits, respectively uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR Figure 2. SO and TSSOP connections 1. See Package mechanical M24512-W M24512-R M24256-BW M24256- section for package dimensions, and how to identify pin-1. Summary description SCL SDA AI04035d 7/31 ...
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... Control (WC) is driven High. When unconnected, the signal is internally read as V Write operations are allowed. When Write Control (WC) is driven High, Device Select and Address bytes are acknowledged, Data bytes are not acknowledged. 8/31 M24512-W, M24512-R, M24256-BW, M24256-BR indicates how the value of the pull-up resistor can be calculated M24xxx ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR 2.5 Supply voltage (V 2.5.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V In order to secure a stable DC supply voltage recommended to decouple the V with a suitable capacitor (usually of the order of 10nF to 100nF) close to the V package pins ...
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... The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. Table 3. Most Significant address Byte b15 b14 Table 4. Least Significant address Byte b7 b6 10/31 M24512-W, M24512-R, M24256-BW, M24256-BR SDA SDA START Input Change Condition MSB ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR 3 Device operation The device supports the I sends data on to the bus is defined transmitter, and any device that reads the data receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization ...
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... Device Select code, it deselects itself from the bus, and goes into Stand-by mode. Table 5. Operating modes Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write 12/31 M24512-W, M24512-R, M24256-BW, M24256-BR (on Serial Data (SDA), most significant bit first). (1) RW bit WC Bytes ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR Figure 6. Write mode sequences with (data write inhibited) WC BYTE WRITE WC PAGE WRITE WC (cont'd) PAGE WRITE (cont'd) ACK ACK DEV SEL BYTE ADDR BYTE ADDR R/W ACK ACK DEV SEL BYTE ADDR BYTE ADDR R/W NO ACK NO ACK DATA IN N Device operation ...
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... This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from bytes (for the M24256-BW and M24256-BR) or from 1 to 128 bytes (for the M24512-W and M24512-R) of data, each of which is acknowledged by the device if Write Control (WC) is Low ...
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... It is therefore recommended to write by packets of 4 bytes in order to benefit from the larger amount of Write cycles. The M24512-W, M24512-R, M24256-BW and M24256-BR devices are qualified at 1 million (1,000,000) Write cycles, using a cycling routine that writes to the device by multiples of 4- bytes ...
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... Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). 16/31 M24512-W, M24512-R, M24256-BW, M24256-BR WRITE Cycle in Progress START Condition ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR 3.11 Read Operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the next byte address. 3.12 Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 9 ...
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... For all Read commands, the device waits, after each byte read, for an acknowledgment th during the 9 bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Stand-by mode. 18/31 M24512-W, M24512-R, M24256-BW, M24256-BR ACK NO ACK DEV SEL DATA OUT R/W ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR 4 Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 5 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied ...
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... Table 9. AC test measurement conditions Symbol C Load Capacitance L Input Rise and Fall Times Input Levels Input and Output Timing Reference Levels Figure 10. AC test measurement I/O waveform 20/31 M24512-W, M24512-R, M24256-BW, M24256-BR Parameter Parameter Parameter Input Levels Timing Reference Levels 0.8V CC 0.2V CC Min. Max. Unit 2 ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR Table 10. Input parameters Symbol C Input Capacitance (SDA Input Capacitance (other pins) IN Input Impedance ( (E2, E1, E0, WC) Input Impedance ( (E2, E1, E0, WC) Pulse width ignored t NS (Input Filter on SCL and SDA ° 400 kHz A 2. Sampled only, not 100% tested. ...
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... Sampled only, not 100% tested avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 3. For a reSTART condition, or following a Write cycle. 22/31 M24512-W, M24512-R, M24256-BW, M24256-BR Test conditions (see Table device in Stand-by mode ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR Table 14. AC characteristics (M24xxx-R, Symbol Alt SCL t t CHCL HIGH t t CLCH LOW (1) t DL1DL2 t t DXCX SU:DAT t t CLDX HD:DAT t t CLQX ( CLQV ( CHDX SU:STA t t DLCL HD:STA t t CHDH SU:STO t t DHDL ...
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... Figure 11. AC Waveforms tCHCL SCL tDLCL SDA In tCHDX START Condition SCL SDA In tCHDH STOP Condition SCL tCLQV SDA Out 24/31 M24512-W, M24512-R, M24256-BW, M24256-BR tCLCH tCLDX tDXCX SDA Change SDA Input tW Write Cycle tCLQX Data Valid tCHDH tDHDL STOP START Condition Condition ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR 7 Package mechanical Figure 12. SO8W – 8 lead Plastic Small Outline, 208 mils body width, package outline 1. Drawing is not to scale. Table 15. SO8W – 8 lead Plastic Small Outline, 208 mils body width, package mechanical data Symbol ...
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... Figure 13. SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Outline A2 1. Drawing is not to scale. 2. Table 16. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data Symbol ccc 26/31 M24512-W, M24512-R, M24256-BW, M24256-BR A ccc millimeters Typ Min Max 1.75 0.10 0.25 1.25 0.28 0.48 0.17 0.23 0.10 4.90 4 ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR Figure 14. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline Drawing is not to scale. Table 17. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data Symbol ...
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... ST Sales Office. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 28/31 M24512-W, M24512-R, M24256-BW, M24256-BR M24512– ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR 9 Revision history Table 19. Document revision history Date Revision 29-Jan-2001 10-Apr-2001 16-Jul-2001 02-Oct-2001 13-Dec-2001 12-Jun-2001 22-Oct-2003 02-Sep-2004 22-Feb-2005 Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated 1.1 LGA8 and SO8(wide) packages added ...
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... CC0 CC1 and Table 12. PDIP8 package removed. Packages are ECOPACK® compliant. Small text changes. M24256-BW and M24256-BR part numbers added. Section 3.9: ECC (Error Correction Code) and Write cycling I and I modified in Table 12: DC characteristics CC CC1 ...
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... M24512-W, M24512-R, M24256-BW, M24256-BR Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...