M24512-RBN6 STMICROELECTRONICS [STMicroelectronics], M24512-RBN6 Datasheet - Page 11

• Manufacturer Part Number: M24512-RBN6
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 9. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
After the successful completion of a Read opera-
tion, the device’s internal address counter is incre-
mented by one, to point to the next byte address.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in
ure
the bus master sends another Start condition, and
repeats the Device Select Code, with the Read/
Write bit (RW) set to 1. The device acknowledges
9.) but without sending a Stop condition. Then,
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
DEV SEL *
DEV SEL *
DEV SEL
DEV SEL
ACK
DATA OUT N
R/W
R/W
R/W
ACK
ACK
ACK
ACK
R/W
NO ACK
DATA OUT 1
BYTE ADDR
BYTE ADDR
DATA OUT
Fig-
NO ACK
ACK
ACK
ACK
BYTE ADDR
BYTE ADDR
this, and outputs the contents of the addressed
byte. The bus master must not acknowledge the
byte, and terminates the transfer with a Stop con-
dition.
Current Address Read
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the Read/Write bit (RW) set
to 1. The device acknowledges this, and outputs
the byte addressed by the internal address
counter. The counter is then incremented. The bus
master terminates the transfer with a Stop condi-
tion, as shown in
the byte.
ACK
ACK
ACK
DATA OUT N
DEV SEL *
DEV SEL *
Figure
st
and 4
NO ACK
R/W
ACK
ACK
R/W
th
9., without acknowledging
bytes) must be identical.
DATA OUT 1
DATA OUT
NO ACK
ACK
AI01105C
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