M24C32-R STMICROELECTRONICS [STMicroelectronics], M24C32-R Datasheet - Page 10

• Manufacturer Part Number: M24C32-R
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24C64, M24C32
Page Write
The Page Write mode allows up to 32 bytes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
that is, the most significant memory address bits
(b12-b5 for M24C64, and b11-b5 for M24C32) are
the same. If more bytes are sent than will fit up to
the end of the row, a condition known as ‘roll-over’
occurs. This should be avoided, as data starts to
become overwritten in an implementation depen-
dent way.
Figure 8. Write Mode Sequences with WC=0 (data write enabled)
10/26
WC
BYTE WRITE
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
DEV SEL
DEV SEL
ACK
DATA IN N
R/W
R/W
ACK
ACK
BYTE ADDR
BYTE ADDR
ACK
The bus master sends from 1 to 32 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca-
tion are not modified, and each data byte is fol-
lowed by a NoAck. After each byte is transferred,
the internal byte address counter (the 5 least sig-
nificant address bits only) is incremented. The
transfer is terminated by the bus master generat-
ing a Stop condition.
ACK
ACK
BYTE ADDR
BYTE ADDR
ACK
ACK
DATA IN 1
DATA IN
ACK
ACK
DATA IN 2
AI01106C