M95M01-RMN6G STMICROELECTRONICS [STMicroelectronics], M95M01-RMN6G Datasheet - Page 21

• Manufacturer Part Number: M95M01-RMN6G
• Description: 1 Mbit serial SPI bus EEPROM with high speed clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M95M01-R
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in
The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
Status Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is
driven High, the self-timed Write Status Register cycle (whose duration is t
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
Figure 10. Write Status Register (WRSR) sequence
S
C
D
Q
0
1
High Impedance
2
Instruction
3
4
5
Figure
6
7
MSB
10.
7
8
6
9 10 11 12 13 14 15
5
Register In
4
Status
3
2
1
0
AI02282D
W
) is initiated.
Instructions
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