M95M01-RMN6G STMICROELECTRONICS [STMicroelectronics], M95M01-RMN6G Datasheet - Page 25

• Manufacturer Part Number: M95M01-RMN6G
• Description: 1 Mbit serial SPI bus EEPROM with high speed clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M95M01-R
6.6
Write to Memory Array (WRITE)
As shown in
Low. The bits of the instruction byte, address byte, and at least one data byte are then
shifted in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) High at a byte boundary of the input
data. In the case of
latched in, indicating that the instruction is being used to write a single byte. The self-timed
Write cycle starts, and continues for a period t
which the Write in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven Low, as shown in
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle. The self-
timed Write cycle starts, and continues, for a period t
end of which the Write in Progress (WIP) bit is reset to 0.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size is 256 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
Figure 12. Byte Write (WRITE) sequence
1. As shown in
S
C
D
Q
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
if a Write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure
Table
0
1
High Impedance
6, the most significant address bits are Don’t Care.
12, to send this instruction to the device, Chip Select (S) is first driven
Figure
2
Instruction
3
4
12, this occurs after the eighth bit of the data byte has been
5
6
7
23
8
14 13
9 10
24-bit address
WC
3
28 29 30 31 32 33 34 35
(as specified in
2
WC
1
(as specified in
0
7
6
Table
5
Figure
Data byte
4
13), at the end of
3
36 37 38
Table
13, the next byte
2
1
13), at the
Instructions
0
39
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