W25Q80BVDAAG WINBOND [Winbond], W25Q80BVDAAG Datasheet - Page 47
![no-image](/images/no-image-200.jpg)
W25Q80BVDAAG
Manufacturer Part Number
W25Q80BVDAAG
Description
8M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI
Manufacturer
WINBOND [Winbond]
Datasheet
1.W25Q80BVDAAG.pdf
(75 pages)
- Current page: 47 of 75
- Download datasheet (2Mb)
9.2.29
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Power-down instruction. The lower power consumption makes the Power-down
instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics).
The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in
figure 27.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down
instruction will not be executed. After /CS is driven high, the power-down state will entered within the time
duration of t
down / Device ID instruction, which restores the device to normal operation, will be recognized. All other
instructions are ignored. This includes the Read Status Register instruction, which is always available
during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition
for securing maximum write protection. The device always powers-up in the normal operation with the
standby current of ICC1.
(IO
CLK
/CS
DI
Power-down (B9h)
0
)
DP
Mode 3
Mode 0
(See AC Characteristics). While in the power-down state only the Release from Power-
0
Figure 27. Deep Power-down Instruction Sequence Diagram
1
Instruction (B9h)
2
3
4
5
6
- 47 -
7
Stand-by current
Publication Release Date: October 06, 2010
tDP
Power-down current
Mode 3
Mode 0
W25Q80BV
Revision D
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