CY62256VLL-70SNE CYPRESS [Cypress Semiconductor], CY62256VLL-70SNE Datasheet

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CY62256VLL-70SNE

Manufacturer Part Number
CY62256VLL-70SNE
Description
256K (32K x 8) Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Cypress Semiconductor Corporation
Document #: 38-05057 Rev. *F
Features
• High Speed
• Temperature Ranges
• Low voltage range:
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in a Pb-free and non Pb-free standard 28-pin
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
— 70 ns
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
— 2.7V – 3.6V
narrow SOIC, 28-pin TSOP-1 and 28-pin Reverse
TSOP-1 packages
Logic Block Diagram
CE
WE
OE
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
198 Champion Court
INPUTBUFFER
DECODER
COLUMN
32K × 8
ARRAY
Functional Description
The CY62256V family is composed of two high-performance
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and Tri-state drivers.
These devices have an automatic power-down feature,
reducing the power consumption by over 99% when
deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
addressed by the address present on the address pins (A
through A
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
POWER
DOWN
0
through I/O
256K (32K x 8) Static RAM
14
San Jose
). Reading the device is accomplished by selecting
7
) is written into the memory location
,
CA 95134-1709
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
[1]
0
1
2
3
4
5
6
7
Revised July 25, 2006
CY62256V
408-943-2600
0
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CY62256VLL-70SNE Summary of contents

Page 1

... Functional Description The CY62256V family is composed of two high-performance CMOS static RAM’s organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and Tri-state drivers. These devices have an automatic power-down feature, reducing the power consumption by over 99% when deselected ...

Page 2

... Product Portfolio Product Range Min. CY62256VLL Com’l/Ind’l 2.7 Automotive Pin Configurations Narrow SOIC Top View ...

Page 3

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ...

Page 4

Capacitance Parameter Description C Input Capacitance IN C Output Capacitance OUT Thermal Resistance Parameter Description Θ Thermal Resistance JA [6] (Junction to Ambient) Θ Thermal Resistance JC [5] (Junction to Case) AC Test Loads and Waveforms ...

Page 5

... L 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. ...

Page 6

Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) ADDRESS PREVIOUS DATA VALID DATA OUT [13, 14] Read Cycle No. 2 (OE Controlled ACE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE SUPPLY ...

Page 7

Switching Waveforms (continued) [10, 15, 16] Write Cycle No. 2 (CE Controlled) ADDRESS CE WE DATA I/O Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS NOTE 17 DATA I/O t HZWE Document #: 38-05057 Rev. ...

Page 8

Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.8 1.6 1.4 1.2 1.0 0 25°C 0.6 A 0.4 0.2 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 2.5 2.0 1 25°C A ...

Page 9

... H High-Z Ordering Information Speed Ordering Code (ns) 70 CY62256VLL-70SNC CY62256VLL-70SNXC CY62256VLL-70ZC CY62256VLL-70ZXC CY62256VLL-70SNXI CY62256VLL-70ZI CY62256VLL-70ZXI CY62256VLL-70ZRI CY62256VLL-70ZRXI CY62256VLL-70SNE CY62256VLL-70SNXE CY62256VLL-70ZE CY62256VLL-70ZXE CY62256VLL-70ZRE CY62256VLL-70ZRXE Please contact your local Cypress sales representative for availability of these parts Document #: 38-05057 Rev. *F (continued) NORMALIZED I 1.25 1.00 0.75 0.50 1 800 1000 ...

Page 10

Package Diagrams 28-pin Thin Small Outline Package Type 1 (8 × 13.4 mm) (51-85071) Document #: 38-05057 Rev. *F 28-pin (300-mil) SNC (Narrow Body) (51-85092) CY62256V 51-85092-*B 51-85071-*G Page [+] Feedback [+] Feedback ...

Page 11

Package Diagrams (continued) 28-pin Reverse Thin Small Outline Package Type 1 (8 × 13.4 mm) (51-85074) All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05057 Rev. *F © Cypress Semiconductor ...

Page 12

Document History Page Document Title: CY62256V, 256K (32K x 8) Static RAM Document Number: 38-05057 Orig. of REV. ECN NO. Issue Date Change ** 107248 09/10/01 *A 111445 11/01/01 *B 115229 05/23/02 *C 116507 09/04/02 *D 239134 See ECN *E ...

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