CY62256VLL-70SNE CYPRESS [Cypress Semiconductor], CY62256VLL-70SNE Datasheet - Page 6

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CY62256VLL-70SNE

Manufacturer Part Number
CY62256VLL-70SNE
Description
256K (32K x 8) Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Document #: 38-05057 Rev. *F
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
Read Cycle No. 2 (OE Controlled)
Write Cycle No. 1 (WE Controlled)
Notes:
12. Device is continuously selected. OE, CE = V
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = V
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
DATA OUT
DATA OUT
CURRENT
ADDRESS
ADDRESS
DATA I/O
SUPPLY
V
WE
CE
OE
CE
OE
CC
NOTE 17
PREVIOUS DATA VALID
HIGH IMPEDANCE
t
PU
IH
t
LZCE
t
.
SA
t
HZOE
[13, 14]
[10, 15, 16]
t
t
IL
ACE
LZOE
.
t
50%
OHA
t
DOE
t
AA
t
AW
[12, 13]
t
RC
t
WC
t
RC
DATA
t
t
PWE
SD
IN
VALID
DATA VALID
DATA VALID
t
HA
t
HD
t
t
HZOE
HZCE
t
PD
50%
CY62256V
IMPEDANCE
Page 6 of 12
HIGH
ICC
ISB
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