NAND01G-N STMICROELECTRONICS [STMicroelectronics], NAND01G-N Datasheet - Page 15

• Manufacturer Part Number: NAND01G-N
• Description: 1 Gbit (x8/x16) 2112 Byte Page NAND Flash Memory and 512 Mbit (x16) LPSDRAM, 1.8V, Multi-Chip Package
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

NAND01G-N
2.19
2.20
2.21
2.22
2.23
2.24
LPSDRAM Clock Input (K)
The Clock signal, K, is used to clock the Read and Write cycles on the LPSDRAM. During
normal operation, the Clock Enable pin, KE, is High, V
suspended to switch the device to the Self-Refresh, Power-Down or Deep Power-Down
mode by driving KE Low, V
LPSDRAM Clock Input (K)
The Clock signal, K, is only available on the DDR LPSDRAM. It is used in conjunction with
the Clock signal, K.
All LPSDRAM input signals except DQM0/DQM1, UDQS/LDQS and DQ0-DQ15 are
referred to the cross point of K rising edge and K falling edge.
LPSDRAM Clock Enable (KE)
The Clock Enable, KE, pin is used by the LPSDRAM to control the synchronizing of the
signals with Clock signal K (and K on DDR LPSDRAM). If KE is High, V
rising edge is valid. When KE is Low, V
and Write cycles are extended. KE is also involved in switching the device to the Self-
Refresh, Power-Down and Deep Power-Down modes.
LPSDRAM Lower/Upper Data Input/Output Mask (DQM0,
DQM1)
Data Mask Enable Inputs are used to mask the Read or Write data.
Lower/Upper Data Read/Write Strobe Input/Output (LDQS,
UDQS)
LDQS and UDQS are only available on the DDR LPSDRAM. They can be either input or
output signals and act as write data strobe and read data strobe respectively. LDQS and
UDQS are the strobe signals for DQ0 to DQ7 and DQ8 to DQ15, respectively.
LPSDRAM V
V
supply for all operations (Read and Write).
DDD
provides the power supply to the internal core of the LPSDRAM. It is the main power
DDD
supply voltage
IL
.
Rev1.0
IL
, the signals are no longer clocked and data Read
IH
. The clock signal K can be
Signals description
IH
, the next Clock
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