M48Z02-150PC1TR STMICROELECTRONICS [STMicroelectronics], M48Z02-150PC1TR Datasheet - Page 8

• Manufacturer Part Number: M48Z02-150PC1TR
• Description: 5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M48Z02, M48Z12
WRITE Mode
The M48Z02/12 is in the WRITE Mode whenever
W and E are active. The start of a WRITE is refer-
enced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of t
from WRITE Enable prior to the initiation of anoth-
Figure 7. WRITE Enable Controlled, WRITE AC Waveform
Figure 8. Chip Enable Controlled, WRITE AC Waveforms
8/16
A0-A10
E
W
DQ0-DQ7
A0-A10
E
W
DQ0-DQ7
EHAX
from Chip Enable or t
tAVEL
tAVEL
tAVWL
tAVWL
tWLQZ
WHAX
tAVWH
tAVEH
tWLWH
tAVAV
tAVAV
VALID
VALID
tELEH
er READ or WRITE cycle. Data-in must be valid t
VWH
t
WRITE cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
after W falls.
WHDX
tDVEH
prior to the end of WRITE and remain valid for
tDVWH
afterward. G should be kept high during
DATA INPUT
DATA INPUT
tWHDX
tEHDX
tWHQX
tEHAX
tWHAX
AI01332B
AI01331
WLQZ
D-