M48Z35-70MH1E STMICROELECTRONICS [STMicroelectronics], M48Z35-70MH1E Datasheet - Page 8

• Manufacturer Part Number: M48Z35-70MH1E
• Description: 256Kbit (32Kbit x 8) ZEROPOWER SRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

2
Note:
2.1
8/23
Operating modes
The M48Z35/Y also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single 5V supply for an out of tolerance condition. When V
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V
approximately 3V, the control circuitry connects the battery which maintains data until valid
power returns.
Table 2.
1. See
X = V
Read mode
The M48Z35/Y is in the READ Mode whenever W (WRITE Enable) is high, E (Chip Enable)
is low. The device architecture allows ripple-through access of data from eight of 264,144
locations in the static storage array. Thus, the unique address specified by the 15 Address
Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within Address Access time (t
signal is stable, providing that the E and G access times are also satisfied. If the E and G
access times are not met, valid data will be available after the latter of the Chip Enable
Access time (t
The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are
activated before t
the Address Inputs are changed while E and G remain active, output data will remain valid
for Output Data Hold time (t
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
IH
Table 6 on page 12
or V
IL
Operating modes
V
; V
ELQV
SO
SO
4.75 to 5.5V
4.5 to 5.5V
to V
AVQV
) or Output Enable Access time (t
= Battery Back-up Switchover Voltage.
V
V
PFD
or
SO
CC
, the data lines will be driven to an indeterminate state until t
for details.
(1)
(min)
AXQX
(1)
) but will go indeterminate until the next Address Access.
V
V
V
V
E
X
X
IH
IL
IL
IL
V
V
G
X
X
X
X
IH
IL
GLQV
V
V
V
W
X
X
X
IH
IH
IL
).
AVQV
CC
DQ0-DQ7
High Z
High Z
High Z
High Z
D
. As V
) after the last address input
D
OUT
IN
CC
CC
falls below
is out of
Battery back-up
CMOS standby
Standby
Power
Active
Active
Active
mode
AVQV
. If