CY14B101K CYPRESS [Cypress Semiconductor], CY14B101K Datasheet - Page 11

• Manufacturer Part Number: CY14B101K
• Description: 1 Mbit (128K x 8) nvSRAM With Real-Time Clock
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 4. Register Map Detail (continued)
Document #: 001-06401 Rev. *E
Calibration
Calibration These five bits control the calibration of the clock.
0x1FFFB
0x1FFFA
0X1FFF8
0x1FFF9
0x1FFF7
OSCEN
WDW
WDS
WDT
Sign
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to 9;
upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0 – 23.
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
contains the upper minutes digit and operates from 0 to 5. The range for the register is 0 – 59.
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
contains the upper digit and operates from 0 to 5. The range for the register is 0 – 59.
Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling the oscillator
saves battery/capacitor power during storage. On a no battery power up, this bit is set to 0.
Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time base.
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no affect. The
bit is cleared automatically once the watchdog timer is reset. The WDS bit is WRITE only. Reading it always returns
a 0.
Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT5–WDT0) so it cannot be
written. This allows the user to strobe the watchdog without disturbing the timeout value. Setting this bit to 0 allows
bits 5 – 0 to be written on the next WRITE to the watchdog register. The new value will be loaded on the next internal
watchdog clock after the WRITE cycle is complete. This function is explained in more detail in the watchdog timer
section.
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents
a multiplier of the 32 Hz count (31.25 ms). The minimum range or timeout value is 31.25 ms (a setting of 1) and the
maximum timeout is 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These
bits can be written only if the WDW bit was cleared to 0 on a previous cycle.
OSCEN
12/24
WDS
D7
D7
D7
D7
D7
0
0
WDW
D6
D6
D6
D6
D6
0
0
10s Seconds
10s Minutes
Calibration
Sign
D5
D5
D5
D5
D5
10s Hours
PRELIMINARY
Time Keeping – Seconds
Time Keeping – Minutes
Time Keeping – Hours
Calibration/Control
WatchDog Timer
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
WDT
Calibration
D2
D2
D2
D2
D2
Seconds
Minutes
Hours
D1
D1
D1
D1
D1
CY14B101K
Page 11 of 24
D0
D0
D0
D0
D0
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