CY14B101K CYPRESS [Cypress Semiconductor], CY14B101K Datasheet - Page 9

• Manufacturer Part Number: CY14B101K
• Description: 1 Mbit (128K x 8) nvSRAM With Real-Time Clock
• Manufacturer: CYPRESS [Cypress Semiconductor]

when the register is READ. If the INT pin is programmed for
level mode, then the condition clears and the INT pin returns
to its inactive state. If the pin is programmed for pulse mode,
then reading the flag also clears the flag and the pin. The pulse
will not complete its specified duration if the Flags/Control
register is READ. If the INT pin is used as a host reset, then
the Flags/Control register should not be READ during a reset.
RTC Recommended Component Configuration
Document #: 001-06401 Rev. *E
Watchdog
Monitor
Alarm
Clock
Power
Timer
VINT
WIE
PFE
WDF
PF
AF
AIE
Figure 4. Interrupt Block Diagram
PRELIMINARY
Driver
Pin
H/L
P/L
During a power on reset with no battery, the interrupt register
is automatically loaded with the value 24h. This causes power
fail interrupt to be enabled with an active LOW pulse.
Flags Register – The Flags register has three flag bits: WDF,
AF, and PF. These flag bits are initialized to 00h. These flags
are set by the watchdog timeout, alarm match, or power fail
monitor respectively. The processor can either poll this register
or enable interrupts to be informed when a flag is set. The flags
are automatically reset once the register is READ.
V
V
SS
CC
Recommended Values
Y1 = 32.768 KHz
RF = 10 M
C
C
1
2
= 0
= 56 pF
INT
Ω
WDF - Watchdog Timer Flag
Enable
WIE - Watchdog Interrupt
PF - Power F ail Flag
AIE - Alarm Interrupt Enable
P/L - Pulse Level
H/L - High/Low
PFE - Power Fail Enable
AF - Alarm Flag
CY14B101K
Page 9 of 24
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