HYB25D256160CC-5 QIMONDA [Qimonda AG], HYB25D256160CC-5 Datasheet
HYB25D256160CC-5
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HYB25D256160CC-5 Summary of contents
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HYB25D256[40/80/16]0CE(L), HYB25D256[40/80/16]0C[T/C/F], HYI25D256[80/16]0C[C/E/F/T] Revision History: 2007-03, Rev. 2.3 Page Subjects (major changes since last revision) All Adapted internet edition 17 Corrected table 7 mode register definition 72 Changed the 1 1.5 mA for low power 85, 86 Changed ...
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Overview This chapter lists all main features of the product family HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) and the ordering information. 1.1 Features • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with ...
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... DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. The 256 Mbit Double-Data-Rate SDRAM operates from a differential clock (CK and CK ...
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Product Type Organization CAS-RCD-RP Standard Temperature Range (0 °C - +70 °C) HYB25D256800CE–5A ×8 HYB25D256160CE–5A ×16 ×8 HYB25D256800CE–5 ×16 HYB25D256160CE–5 ×8 HYB25D256800CE–6 HYB25D256800CEL–6 ×8 ×16 HYB25D256160CE–6 HYB25D256160CEL–6 ×16 ×4 HYB25D256400CE–7 ×4 HYB25D256400CF–5 ×8 HYB25D256800CF–5 ×16 HYB25D256160CF–5 ×4 HYB25D256400CF–6 ×8 ...
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... HYB25D256400CT–7 ×4 HYB25D256400CC–5 ×8 HYB25D256800CC–5 ×16 HYB25D256160CC–5 ×4 HYB25D256400CC–6 ×8 HYB25D256800CC–6 ×16 HYB25D256160CC–6 Industrial Temperature Range (–40 °C - +85 °C) ×8 HYI25D256800CT–5 ×16 HYI25D256160CT–5 ×8 HYI25D256800CT–6 ×16 HYI25D256160CT–6 ×8 HYI25D256800CC–5 × ...
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Pin Configuration The pin configuration of a DDR SDRAM is listed by function in column are explained in Table 5 and Table 6 TSOP package in Figure 2. Ball#/Pin# Name Pin Type Clock Signals G2 G3, ...
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Ball#/Pin# Name Pin Type Data Signals ×4 Organization B7, 5 DQ0 I/O D7, 11 DQ1 I/O D3, 56 DQ2 I/O B3, 62 DQ3 I/O Data Strobe ×4 Organisation E3, 51 DQS I/O Data Mask ×4 Organization F3 ...
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Ball#/Pin# Name Pin Type Data Strobe ×16 organization E3, 51 UDQS I/O E7, 16 LDQS I/O Data Mask ×16 organization F3, 47 UDM I F7, 20 LDM I Power Supplies V F1 REF V A9, B2, C8, D2, ...
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Ball#/Pin# Name Pin Type F9, 14, 17, 19 25,43, 50, 53 Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is ...
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Pin Configuration P-TFBGA-60 Top View, see the balls throught the package Rev. 2.3, 2007-03 03062006-8CCM-VPUW HY[B/I]25D256[16/40/80]0C[E/C/F/T]( ...
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Rev. 2.3, 2007-03 03062006-8CCM-VPUW HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM Pin Configuration P-TSOPII-66-1 12 Internet Data Sheet FIGURE 2 ...
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... Functional Description The 256 Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. The 256 Mbit Double-Data-Rate SDRAM is internally configured as a quad-bank DRAM. The 256 Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double- data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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Field Bits Type Description BL [2:0] W Burst Length Number of sequential bits per DQ related to one read/write command. Note: All other bit combinations are RESERVED. 001 2 B 010 4 B 011 Burst ...
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Burst Length Starting Column Address — — 0 — — — — — — ...
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Field Bits Type Description DLL 0 W DLL Status Drive Strength MODE [12:2] W Operating Mode Note: All other bit combinations are RESERVED. 00000000000 write ...
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Name (Function) Deselect (NOP) No Operation (NOP) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) ...
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Current State CKE n-1 CKEn Previous Cycle Current Cycle Self Refresh L L Self Refresh L H Power Down L L Power Down L H All Banks Idle H L All Banks Idle H L Bank(s) Active H L — ...
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Current State CS RAS CAS WE Any Idle Row Active ...
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Truth Table 4: Current State Bank n - Command to Bank m (different bank) Current State CS RAS CAS WE Any Idle Row Activating Active ...
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Concurrent Auto Precharge: This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt ...
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Electrical Characteristics This chapter lists the electrical characteristics. 4.1 Operating Conditions This chapter contains the operating conditions tables. Parameter V Voltage on I/O pins relative Voltage on inputs relative Voltage on supply ...
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Parameter Input Capacitance: CK, CK Delta Input Capacitance Input Capacitance: All other input-only pins Delta Input Capacitance: All other input-only pins Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS These values are not subject to production ...
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Parameter Symbol V Device Supply Voltage DD V Device Supply Voltage DD V Output Supply Voltage DDQ V Output Supply Voltage DDQ V V Supply Voltage, I/O Supply , SS SSQ Voltage V Input Reference Voltage REF V I/O Termination ...
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AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Specifications and Conditions, and Electrical Characteristics and AC Timing.) Notes V 1. All voltages referenced Tests ...
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Parameter Input High (Logic 1) Voltage, DQ, DQS and DM Signals Input Low (Logic 0) Voltage, DQ, DQS and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK Inputs V = 2.5 V ...
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Parameter Symbol t DQS falling edge hold time from DSH CK (write cycle) t DQS falling edge to CK setup time DSS (write cycle) t Clock Half Period HP t Data-out high-impedance time HZ from CK/CK t Address and control ...
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Parameter Symbol t Internal write to read command WTR delay t Exit self-refresh to non-read XSNR command t Exit self-refresh to read command XSRD 1) 0 °C ≤ T ≤ 70 ° 2.5 V ± 0.2 V, ...
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Parameter DQS-DQ skew (DQS and associated DQ signals) st Write command to 1 DQS latching transition DQ and DM input setup time DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) ...
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Parameter Exit self-refresh to non-read command Exit self-refresh to read command V = 2.5 V ± 0 +2.5 V ± 0 °C ≤ 1) DDQ DD 2) Input slew rate ≥1 V/ns 3) The ...
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Parameter Operating Current: one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page ...
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Symbol –5 –6 DDR400B DDR333 Typ. Max. Typ DD0 100 70 DD1 95 110 DD2P DD2F DD2Q I ...
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Package Outlines There are two package types used for this product family each in lead-free and lead-containing assembly: • P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package Description Ball Size Recommended Landing Pad Recommended Solder Mask Rev. 2.3, 2007-03 ...
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P(G)-TFBGA-60: Plastic (non-green/green) Thin Fine Ball Grid Array Rev. 2.3, 2007-03 03062006-8CCM-VPUW HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM Package Outline of P-TFBGA-60-12 (non-green/green) 34 Internet Data Sheet FIGURE 4 ...
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Rev. 2.3, 2007-03 03062006-8CCM-VPUW HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM Package Outline of P-TSOPII-66-1 (non-green/green) 35 Internet Data Sheet FIGURE 5 ...
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List of Figures Figure 1 Pin Configuration P-TFBGA-60 Top View, see the balls throught the package . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 Performance of –5, –6 and – ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Edition 2007-03 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...