HYB18L128160BC-7.5 QIMONDA [Qimonda AG], HYB18L128160BC-7.5 Datasheet

Page 1

...

Page 2

... HYB18L128160BF-7.5; HYE18L128160BF-7.5; HYB18L128160BC-7.5; HYE18L128160BC-7.5 Revision History: Rev. 1.71 All New Qimonda Template Previous Revision: 1.70 all new template (logo) changed to 1.70V-1.95V V V all , DD DDQ Previous Revision: 1.61 2 added disclaimer 49 Figure 47: Updated 28 Figure 25: Updated 12 Chapter 2.1: added to note 6: Programming of the Extended Mode Register... 14 Extended Mode Register table: Editorial changes Chapter 2 ...

Page 3

... Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor • Power-Down and Deep Power Down modes Table 1 Performance Part Number Speed Code Speed Grade Access Time (t ) AC.max Clock Cycle Time (t ) CK.min Table 2 Memory Addressing Scheme Item Banks Rows Columns Data Sheet HY[B/E]18L128160B[C/F]-7.5 = 1.70V to 1.95V DDQ /I ) DD2 DD3 133 ...

Page 4

... Table 3 Ordering Information Type Package Commercial Temperature Range P-VFBGA-54-2 133 MHz 4 Banks × 2 Mbit × 16 LP-SDRAM HYB18L128160BC-7.5 Extended Temperature Range P-VFBGA-54-2 133 MHz 4 Banks × 2 Mbit × 16 LP-SDRAM HYE18L128160BC-7.5 Table 4 Ordering Information for Green Products 1) Type Package Commercial Temperature Range P-VFBGA-54-2 133 MHz 4 Banks × 2 Mbit × 16 LP-SDRAM HYB18L128160BF-7 ...

Page 5

... Description The HY[B/E]18L128160B[C/ high-speed CMOS, dynamic random-access memory containing 134,217,728 bits internally configured as a quad-bank DRAM. The HY[B/E]18L128160B[C/F] achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are burst-oriented ...

Page 6

... RAS CAS WE Mode Registers 12 A0-A11 14 BA0,BA1 2 Column Address 9 Counter / Latch Figure 2 Functional Block Diagram Data Sheet Bank 2 Bank 1 Bank 0 Memory Array 12 4096 (4096 x 512 x 16) Sense Amplifier IO Gating 2 DQM Mask Logic Column Decoder 9 6 HY[B/E]18L128160B[C/F]-7.5 128-Mbit Mobile-RAM OverviewDescription Bank LDQM ...

Page 7

... SELF REFRESH. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple memory banks considered part of the command code. RAS, CAS, Input Command Inputs: RAS, CAS and WE (along with CS) define the command being WE entered ...

Page 8

... Functional Description The 128-Mbit Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits internally configured as a quad-bank DRAM. READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command ...

Page 9

At first, device core power (V ) and device IO power (V DD and V are driven from a single power converter output. DDQ Assert and hold CKE and DQM to a HIGH level. 2. After V and V ...

Page 10

Field Bits Type Description BL [2:0] w Burst Length 000 1 B 001 2 B 010 4 B 011 8 B 111 full page (Sequential burst type only) B Note: All other bit combinations are RESERVED. 2.2.1.1 Burst Length READ ...

Page 11

Whenever a boundary of the block is reached within a given sequence, the following access wraps within the block. 2.2.1.2 Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred ...

Page 12

... Partial Array Self Refresh is a power-saving feature specific to Mobile RAMs. With PASR, self refresh may be restricted to variable portions of the total array. The selection comprises all four banks, two banks, one bank, half of one bank, and a quarter of one bank. Data written to the non activated memory sections will get lost after a period defined by t (cf ...

Page 13

Figure 4 State Diagram Data Sheet HY[B/E]18L128160B[C/F]-7.5 128-Mbit Mobile-RAM Functional DescriptionState Diagram 13 05282004-NZNK-8T0D Rev. 1.71, 2007-01 ...

Page 14

... DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read cycles; DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are placed in High-Z state (two clocks latency) during read cycles. ...

Page 15

Figure 5 Address / Command Inputs Timing Parameters Table 8 Inputs Timing Parameters Parameter Clock cycle time Clock frequency Clock high-level width Clock low-level width Address and command input setup time Address and command input hold time 2.4.1 NO OPERATION ...

Page 16

DESELECT The DESELECT function (CS = HIGH) prevents new commands from being executed by the Mobile-RAM. The Mobile-RAM is effectively deselected. Operations already in progress are not affected. 2.4.3 MODE REGISTER SET Figure 7 Mode Register Set Command The ...

Page 17

ACTIVE Figure 9 ACTIVE Command Before any READ or WRITE commands can be issued to a bank within the Mobile-RAM, a row in that bank must be “opened” (activated). This is accomplished via the ACTIVE command and addresses A0 ...

Page 18

Table 10 Timing Parameters for ACTIVE Command Parameter ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE bank A to ACTIVE bank B delay 1) These parameters account for the number of clock cycles and depend on ...

Page 19

Figure 12 Basic READ Timing Parameters for DQs Data Sheet HY[B/E]18L128160B[C/F]-7.5 128-Mbit Mobile-RAM Functional DescriptionCommands 19 05282004-NZNK-8T0D Rev. 1.71, 2007-01 ...

Page 20

Table 11 Timing Parameters for READ Parameter Access time from CLK DQ low-impedance time from CLK DQ high-impedance time from CLK Data out hold time DQM to DQ High-Z delay (READ Commands) ACTIVE to ACTIVE command period ACTIVE to READ ...

Page 21

Figure 14 Single READ Burst (CAS Latency = 3) Data from any READ burst may be concatenated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. A READ command can be ...

Page 22

Figure 16 Random READ Bursts Non-consecutive READ bursts are shown in Figure 17 Non-Consecutive READ Bursts Data Sheet HY[B/E]18L128160B[C/F]-7.5 Functional DescriptionCommands Figure 17. 22 128-Mbit Mobile-RAM Rev. 1.71, 2007-01 05282004-NZNK-8T0D ...

Page 23

READ Burst Termination Data from any READ burst may be truncated using the BURST TERMINATE command (see that Auto Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the BURST TERMINATE command must ...

Page 24

Figure 19 Clock Suspend Mode for READ Bursts 2.4.5.3 READ - DQM Operation DQM may be used to suppress read data and place the output buffers into High-Z state. The generic timing parameters as listed in Table 11 also apply ...

Page 25

WRITE command, as shown in a write mask: when asserted HIGH, input data will be masked and no write will be performed. Figure 21 READ to WRITE Timing 2.4.5.5 READ to PRECHARGE A READ burst may be ...

Page 26

Figure 22 READ to PRECHARGE Timing 2.4.6 WRITE Figure 23 WRITE Command WRITE bursts are initiated with a WRITE command, as shown in in Figure 24; they apply to all write operations. The starting column and bank addresses are provided ...

Page 27

For the generic WRITE commands used in the following illustrations, Auto Precharge is disabled. Figure 24 Basic WRITE Timing Parameters for DQs During WRITE bursts, the first valid data-in element is registered coincident with the ...

Page 28

Table 12 Timing Parameters for WRITE Parameter DQ and DQM input setup time DQ input hold time DQM input hold time DQM write mask latency ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay ACTIVE to PRECHARGE command ...

Page 29

Figure 26 WRITE Burst (CAS Latency = 3) Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. A WRITE command can ...

Page 30

Figure 28 Random WRITE Bursts Non-consecutive WRITE bursts are shown in Figure 29 Non-Consecutive WRITE Bursts 2.4.6.1 WRITE Burst Termination Data from any WRITE burst may be truncated using the BURST TERMINATE command (see that Auto Precharge was not activated. ...

Page 31

Figure 30 Terminating a WRITE Burst 2.4.6.2 Clock Suspend Mode for WRITE Cycles Clock suspend mode allows to extend any WRITE burst in progress by a variable number of clock cycles. As long as CKE is registered LOW, the following ...

Page 32

WRITE - DQM Operation DQM may be used to mask write data: when asserted HIGH, input data will be masked and no write will be performed. The generic timing parameters as listed in in progress is not affected and ...

Page 33

WRITE to PRECHARGE A WRITE burst may be followed by, or truncated with a PRECHARGE command to the same bank, provided that Auto Precharge was not activated. This is shown in The PRECHARGE command should be issued t the ...

Page 34

BURST TERMINATE Figure 35 BURST TERMINATE Command The BURST TERMINATE command is used to truncate READ or WRITE bursts (with Auto Precharge disabled). The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be ...

Page 35

The PRECHARGE command is used to deactivate (close) the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (t command is issued. Input ...

Page 36

Figure 37 READ with Auto Precharge Interrupted by READ Figure 38 READ with Auto Precharge Interrupted by WRITE Figure 39 WRITE with Auto Precharge Interrupted by READ Data Sheet HY[B/E]18L128160B[C/F]-7.5 128-Mbit Mobile-RAM Functional DescriptionCommands 36 05282004-NZNK-8T0D Rev. 1.71, 2007-01 ...

Page 37

Figure 40 WRITE with Auto Precharge Interrupted by WRITE Data Sheet HY[B/E]18L128160B[C/F]-7.5 128-Mbit Mobile-RAM Functional DescriptionCommands 37 05282004-NZNK-8T0D Rev. 1.71, 2007-01 ...

Page 38

AUTO REFRESH and SELF REFRESH The Mobile-RAM requires a refresh of all rows in a rolling interval. Each refresh is generated in one of two ways explicit AUTO REFRESH command internally timed event in ...

Page 39

SELF REFRESH Figure 43 SELF REFRESH Entry Command The SELF REFRESH command can be used to retain data in the Mobile-RAM, even if the rest of the system is powered down. When in the self refresh mode, the Mobile-RAM ...

Page 40

Table 14 Timing Parameters for AUTO REFRESH and SELF REFRESH Parameter ACTIVE to ACTIVE command period PRECHARGE command period Refresh period (4096 rows) Self refresh exit time 1) These parameters account for the number of clock cycles and depend on ...

Page 41

... The deep power down mode is an unique function on Low Power SDRAM devices with extremely low current consumption. Deep power down mode is entered using the BURST TERMINATE command (cf. that CKE is LOW. All internal voltage generators inside the device are stopped and all memory data is lost in this mode. To enter the deep power down mode all banks must be precharged. ...

Page 42

Table 15 Current State Bank n - Command to Bank n (cont’d) Current State CS RAS CAS WE Command / Action Read (Auto Precharge Disabled Write L H ...

Page 43

Table 16 Current State Bank n - Command to Bank m (different bank) Current State CS RAS CAS WE Command / Action Any Idle Row Activating ...

Page 44

READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and READs or WRITEs with Auto Precharge disabled. 8) Requires appropriate DQM masking. 9) Concurrent Auto Precharge: bank n will start precharging when ...

Page 45

Electrical Characteristics 3.1 Operating Conditions Table 18 Absolute Maximum Ratings Parameter Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operation Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Attention: Stresses above those ...

Page 46

Table 20 Electrical Characteristics Parameter Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input high voltage Input low voltage Output high voltage (I = -0.1 mA) OH Output low voltage (I = 0.1 mA) OL Input leakage current ...

Page 47

Table 21 AC Characteristics Parameter WRITE recovery time PRECHARGE command period Refresh period (4096 rows) Self refresh exit time 1) 0 °C ≤ T ≤ 70 °C (comm.); -25 °C ≤ All parameters assumes proper device ...

Page 48

Operating Currents Table 22 Maximum Operating Currents Parameter & Test Conditions Operating current: one bank: active / read / precharge Precharge power-down standby current: all banks idle, CS ≥ CKE ≤ V IHmin ...

Page 49

Table 23 Self Refresh Currents Parameter & Test Conditions Self Refresh Current: Self refresh mode, full array activation (PASR = 000) Self Refresh Current: Self refresh mode, half array activation (PASR = 001) Self Refresh Current: Self refresh mode, quarter ...

Page 50

Package Outlines Figure 48 P-VFBGA-54-2 (Plastic Very Thin Fine Ball Grid Array Package) You can find all of our packages, sorts of packing and others in our Qimonda Internet http://www.Qimonda.com/products. SMD = Surface Mounted Device Data Sheet HY[B/E]18L128160B[C/F]-7.5 Page ...

Page 51

List of Figures Figure 1 Standard Ballout 128-Mbit Mobile-RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 52

... List of Tables Table 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 2 Memory Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 4 Ordering Information for Green Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 5 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 6 Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 7 Command Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8 Inputs Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 9 Timing Parameters for Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10 Timing Parameters for ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11 Timing Parameters for READ ...

Page 53

Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 54

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 55

Edition 2007-01 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ...