CY14E064L-SZ25XC CYPRESS [Cypress Semiconductor], CY14E064L-SZ25XC Datasheet - Page 2
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CY14E064L-SZ25XC
Manufacturer Part Number
CY14E064L-SZ25XC
Description
64 Kbit (8K x 8) nvSRAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY14E064L-SZ25XC.pdf
(17 pages)
Pin Configurations
Pin Definitions
Document Number: 001-06543 Rev. *D
Pin Name
DQ0-DQ7 Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation.
A
V
HSB
0
V
V
WE
OE
CE
–A
CAP
SS
CC
12
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress.
Power Supply
Power Supply
IO Type
Ground
Input
Input
Input
Input
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
Write Enable Input, Active LOW. When selected LOW, writes data on the IO pins to the address
location latched by the falling edge of CE.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the IO pins to tri-state.
Ground for the Device. The device is connected to ground of the system.
Power Supply Inputs to the Device.
When pulled low external to the chip, it initiates a non-volatile STORE operation. A weak internal pull
up resistor keeps this pin high if not connected (connection optional).
AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
non-volatile elements.
V
DQ0
DQ1
DQ2
V
A
CAP
A
A
A
A
A
A
A
A
SS
12
5
4
3
2
7
6
1
0
11
12
13
4
6
10
14
1
2
3
5
8
7
9
28-SOIC
(Not To Scale)
Top View
Description
HSB
OE
A
CE
DQ7
DQ6
DQ5
DQ4
DQ3
V
WE
A
A
A
CC
8
9
11
10
CY14E064L
Page 2 of 17
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