CY14E256L CYPRESS [Cypress Semiconductor], CY14E256L Datasheet - Page 2

• Manufacturer Part Number: CY14E256L
• Description: 256-Kbit (32K x 8) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 001-06968 Rev. *C
Pin Configurations
Pin Definitions
Pin Name
DQ0-DQ7 Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation.
A
V
HSB
0
V
V
WE
CE
OE
NC
–A
CAP
SS
CC
14
Power Supply Power Supply inputs to the device.
Power Supply Autostore
Input/Output Hardware Store Busy. When low this output indicates a Hardware Store is in progress. When pulled
No Connect No Connects. This pin is not connected to the die.
I/O Type
Ground
Input
Input
Input
Input
Address Inputs used to select one of the 32,768 bytes of the nvSRAM.
Write Enable Input, active LOW. When selected LOW, enables data on the I/O pins to be written to
the address location latched by the falling edge of CE.
Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tri-state.
Ground for the device. Should be connected to ground of the system.
low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull-up resistor
keeps this pin high if not connected. (Connection Optional)
nonvolatile elements.
®
Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
V
DQ
DQ
V
DQ
NC
CAP
A
A
A
A
A
A
A
A
A
A
SS
14
12
7
6
5
4
3
2
1
0
0
1
2
1
3
4
5
6
7
8
10
11
12
13
14
15
16
PRELIMINARY
2
9
32 - Lead SOIC
Top View
(Not To Scale)
Description
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
HSB
WE
OE
NC
CE
DQ
DQ
DQ
DQ
DQ
A
A
A
A
A
11
CC
13
8
9
10
6
5
4
3
7
CY14E256L
Page 2 of 16
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