W9812G6GH-6 WINBOND [Winbond], W9812G6GH-6 Datasheet - Page 38

• Manufacturer Part Number: W9812G6GH-6
• Description: 2M X 4 BANKS X 16 BITS SDRAM
• Manufacturer: WINBOND [Winbond]

11.19
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
(2) Write cycle
(1) Read cycle
(a) CAS latency =2
(b) CAS latency =3
(a) CAS latency =2
(b) CAS latency =3
Timing Chart of Burst Stop Cycle (Burst Stop Command)
(2) Write cycle
(1) Read cycle
Command
Command
Command
Command
( a ) CAS latency =2
( b )CAS latency = 3
DQ
DQM
DQ
DQM
DQ
DQ
Command
Command
Command
Write
DQ
DQ
DQ
Read
Read
Write
Q0
Q0
0
Read
Read
Write
Q0
0
Q1
Q1
1
Q1
1
Note:
Q0
Q2
Q0
2
Q2
Q2
2
BST
Q0
Q3
Q1
3
Q1
Q0
3
Q3
Q3
represents the Burst stop command
Q1
Q4
Q2
4
- 38 -
Q2
Q1
4
Q4
Q4
BST
BST
BST
Q2
Q3
5
PRCG
PRCG
Q3
Q2
tWR
tWR
5
Q3
Q4
6
PRCG
PRCG
Q4
Q4
Q3
6
7
Publication Release Date:Aug. 13, 2007
8
Q4
7
9
8
W9812G6GH
10
9
11
10
Revision A06
11