X28HC256D-90 INTERSIL [Intersil Corporation], X28HC256D-90 Datasheet - Page 7

• Manufacturer Part Number: X28HC256D-90
• Description: 5V, Byte Alterable EEPROM
• Manufacturer: INTERSIL [Intersil Corporation]

The Toggle Bit I/O
¬
The Toggle Bit can eliminate the chore of saving and fetching
the last address and data in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28HC256 memories that is frequently updated.
The timing diagram in Figure 4 illustrates the sequence of
events on the bus. The software flow diagram in Figure 5
illustrates a method for polling the Toggle Bit.
FIGURE 5. TOGGLE BIT SOFTWARE FLOW
I/O
WE
CE
OE
FROM ADDR n
6
LOAD ACCUM
ACCUM WITH
LAST WRITE
COMPARE
COMPARE
X28C256
LAST
WRITE
READY
ADDR n
OK?
YES
YES
6
7
NO
*
V
FIGURE 4. TOGGLE BIT BUS SEQUENCE
OH
* I/O
6
Beginning and ending state of I/O
V
OL
X28HC256
Hardware Data Protection
The X28HC256 provides two hardware features that protect
nonvolatile data from inadvertent writes.
• Default V
• Write Inhibit—Holding either OE LOW, WE HIGH, or CE
Software Data Protection
The X28HC256 offers a software-controlled data protection
feature. The X28HC256 is shipped from Intersil with the
software data protection NOT ENABLED; that is, the device
will be in the standard operating mode. In this mode data
should be protected during power-up/down operations
through the use of external circuits. The host would then
have open read and write access of the device once V
was stable.
The X28HC256 can be automatically protected during
power-up and power-down (without the need for external
circuits) by employing the software data protection feature.
The internal software data protection circuit is enabled after
the first write operation, utilizing the software algorithm. This
circuit is nonvolatile, and will remain set for the life of the
device unless the reset command is issued.
Once the software protection is enabled, the X28HC256 is
also protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be
issued prior to writing additional data to the device.
V
HIGH will prevent an inadvertent write cycle during power-
up and power-down, maintaining data integrity.
HIGH Z
CC
is 3.5V typically.
CC
6
Sense—All write functions are inhibited when
will vary.
*
X28C512, X28C513
READY
May 7, 2007
FN8108.2
CC