AT45DB011D-MU ATMEL [ATMEL Corporation], AT45DB011D-MU Datasheet - Page 25

• Manufacturer Part Number: AT45DB011D-MU
• Description: 1-megabit 2.7-volt DataFlash
• Manufacturer: ATMEL [ATMEL Corporation]

13. “Power of 2” Binary Page Size Option
13.1
14. Manufacturer and Device ID Read
3639B–DFLASH–02/07
Programming the Configuration Register
“Power of 2” binary page size Configuration Register is a user-programmable nonvolatile regis-
ter that allows the page size of the main memory to be configured for binary page size
(256 bytes) or the DataFlash standard page size (264 bytes). The “power of 2” page size is a
One-time Programmable (OTP) register and once the device is configured for “power of
2” page size, it cannot be reconfigured again. The devices are initially shipped with the page
size set to 264 bytes.
To program the Configuration Register for “power of 2” binary page size, the CS pin must first be
asserted as it would be with any other command. Once the CS pin has been asserted, the
appropriate 4-byte opcode sequence must be clocked into the device in the correct order. The
4-byte opcode sequence must start with 3DH and be followed by 2AH, 80H, and A6H. After the
last bit of the opcode sequence has been clocked in, the CS pin must be deasserted to initiate
the internally self-timed program cycle. The programming of the Configuration Register should
take place in a time of t
busy. The device must be power-cycled after the completion of the program cycle to set the
“power of 2” page size. If the device is powered-down before the completion of the program
cycle, then setting the Configuration Register cannot be guaranteed. However, the user should
check bit 0 of the status register to see whether the page size was configured for binary page
size. If not, the command can be re-issued again.
Figure 13-1. Erase Sector Protection Register
Identification information can be read from the device to enable systems to electronically query
and identify the device while it is in system. The identification method and the command opcode
comply with the JEDEC standard for “Manufacturer and Device ID Read Methodology for SPI
Compatible Serial Interface Memory Devices”. The type of information that can be read from the
device includes the JEDEC defined Manufacturer ID, the vendor specific Device ID, and the ven-
dor specific Extended Device Information.
To read the identification information, the CS pin must first be asserted and the opcode of 9FH
must be clocked into the device. After the opcode has been clocked in, the device will begin out-
putting the identification data on the SO pin during the subsequent clock cycles. The first byte
that will be output will be the Manufacturer ID followed by two bytes of Device ID information.
The fourth byte output will be the Extended Device Information String Length, which will be 00H
indicating that no Extended Device Information follows. As indicated in the JEDEC standard,
reading the Extended Device Information String Length and any subsequent data is optional.
Deasserting the CS pin will terminate the Manufacturer and Device ID Read operation and put
the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not
require that a full byte of data be read.
Command
Power of Two Page Size
CS
SI
P
, during which time the Status Register will indicate that the device is
Each transition
represents 8 bits
Opcode
Byte 1
Opcode
Byte 2
AT45DB011D [Preliminary]
Byte 1
Opcode
3DH
Byte 3
Opcode
Byte 4
Byte 2
2AH
Byte 3
80H
Byte 4
A6H
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