HYB18T512400AF INFINEON [Infineon Technologies AG], HYB18T512400AF Datasheet
HYB18T512400AF
Related parts for HYB18T512400AF
HYB18T512400AF Summary of contents
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H YS72 T 640 00 [G YS72 T 128 00 0[ G/H] R-x-A H YS72 T 128 02 0[ G/H] R-x-A H YS72 T 256 02 0[ G/H] R-x-A H YS72 T 256 22 0[ ...
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... The memory array is designed with 512Mb Double Data Rate (DDR2) Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution ...
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Ordering Information Product Type Compliance Code PC2-3200 (DDR2-400) HYS72T64000GR-5-A PC2-3200R-333-11-A HYS72T128020GR-5-A PC2-3200R-333-11-B HYS72T128000GR-5-A PC2-3200R-333-11-C HYS72T256220GR-5-A PC2-3200R-333-11 HYS72T256020GR-5-A PC2-3200R-333-11 PC2-4300 (DDR2-533) HYS72T64000GR-3.7-A PC2-4300R-444-11-A HYS72T128020GR-3.7-A PC2-4300R-444-11-B HYS72T128000GR-3.7-A PC2-4300R-444-11-C HYS72T256020GR-3.7-A PC2-4300R-444-11 PC2-3200 (DDR2-400) HYS72T64000HR-5-A PC2-3200R-333-11-A HYS72T128020HR-5-A PC2-3200R-333-11-B HYS72T128000HR-5-A PC2-3200R-333-11-C HYS72T256220HR-5-A PC2-3200R-333-11 HYS72T256020HR-5-A ...
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... HYB18T512800AC HYB18T512800AF 1024 MB HYB18T512400AC HYB18T512400AF 2048 MB HYB18T512400AC HYB18T512400AF 2048 MB HYB18T512400AC HYB18T512400AF For a detailed description of all functionalities of the DRAM components on these modules see the referenced component data sheet 1.4 Pin Definition and Function Pin Name Description A[13:0] Row Address Inputs A11, A[9:0] Column Address Inputs ...
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Pin Configuration PIN# Symbol PIN# 1 VREF 121 2 VSS 122 3 DQ0 123 4 DQ1 124 5 VSS 125 6 DQS0 126 7 DQS0 127 8 VSS 128 9 DQ2 129 10 DQ3 130 11 VSS 131 12 ...
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Pin Configuration (cont’d) PIN# Symbol PIN# 41 VSS 161 42 CB0 162 43 CB1 163 44 VSS 164 45 DQS8 165 46 DQS8 166 47 VSS 167 48 CB2 168 49 CB3 169 50 VSS 170 51 VDDQ 171 52 ...
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... When sampled at the positive edge of the clock, RAS, CAS and WE define the operation to be executed by the SDRAM. Selects which internal SDRAM memory bank is activated During Bank Activate command cycle, Address defines the row address. During a Read or Write command cycle, Address defines the column address. In addition to the column address, A10(=AP) is used to invoke Auto-Precharge operation at the end of the burst read or write cycle ...
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Block Diagrams 2.1 One Rank 64M x 72 (512 MByte) DDR2 SDRAM DIMM Module (x8 components) HYS72T64000[G/H] on Raw Card A RS0 DQS0 DQS0 DM0/DQS9 NU/ DQS9 RDQS DQ0 I/O 0 DQ1 I/O 1 DQ2 I/O 2 DQ3 I/O ...
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Block Diagrams (cont’d) 2.2 128M x 72 (1GByte) two rank DDR2 SDRAM DIMM Modules (x8 components) HYS72T128020[G/H] on Raw Card B RS1 RS0 DQS0 DQS0 DM0/DQS9 NU/ DM/ CS DQS DQS DQS9 RDQS RDQS DQ0 I/O 0 DQ1 I/O 1 ...
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Block Diagrams (cont’d) 2.3 One Rank 128M GByte) DDR2 SDRAM DIMM Modules (x4 components) HYS72T128000[G/H] on Raw Card C VSS RS0 DQS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS1 DQS0 DQ8 DQ9 DQ10 DQ11 DQS2 DQS2 DQ16 DQ17 ...
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Block Diagrams (cont’d) 2.4 256M GByte) two rank DDR2 SDRAM DIMM Modules (x4 components) HYS72T256020[G/H] / HYS72T256220[G/H] RS1 VSS RS0 DQS0 DQS0 DM CS DQS DQS DQ0 I/O 0 DQ1 I/O 1 DQ2 I/O 2 DQ3 I/O ...
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Absolute Maximum Ratings Parameter Voltage on any pins relative to V Voltage on V relative Voltage on V relative Storage temperature range Stresses greater than those listed under “Absolute Maximum ...
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I Specifications and Conditions DD 4.1 512 MByte Registered Module HYS72T64000[G/H] (one rank, nine components x8) 512 MByte HYS72T64000[G/H] Symbol Parameter / Condition I Operating Current DD0 I Operating Current DD1 I Precharge PD Standby Current DD2P I Precharge ...
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Mbyte Registered Module HYS72T128000[G/H] (one rank, 18 components x4) 1024 MByte HYS72T128000[G/H] Symbol Parameter / Condition I Operating Current DD0 I Operating Current DD1 I Precharge PD Standby Current DD2P I Precharge Standby Current DD2N I Precharge Quiet ...
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I Measurement Conditions 1.8V 0.1V 1.8V DD DDQ Symbol Operating Current - One bank Active - Precharge CKmin. RC RCmin., DD0 inputs are SWITCHING, Databus ...
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I Measurement Conditions (cont’d) DD For testing the IDD parameters, the following timing parameters are used: Parameter CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to ...
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Electrical Characteristics & AC Timings 5.1 AC Timing Parameter by Speed Grade Symbol Parameter t DQ output access time from DQS output access time from DQSCK t CK, CK high-level width ...
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Symbol Parameter Active to Read or Write delay (with and without Auto-Pre- t RCD charge) delay t Precharge command period RP Active bank A to Active bank t RRD B command t CAS A to CAS B Command Period CCD ...
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... SPD Codes for PC2–4300R (–3.7) Product Type Organization Label Code Jedec SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used ...
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Product Type Organization Label Code Jedec SPD Revision Byte# Description t 29 [ns] RCD.min t 30 [ns] RAS.min 31 Module Density per Rank 32 t and t [ns] AS.min CS.min and [ns] AH.min CH.min t 34 [ns] ...
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Product Type Organization Label Code Jedec SPD Revision Byte# Description Toggle Rate REG 62 SPD Revision 63 Checksum of Bytes 0-62 64 JEDEC ID Code of Infineon (1) 65 JEDEC ID Code of Infineon (2) 66 JEDEC ...
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Product Type Organization Label Code Jedec SPD Revision Byte# Description 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) ...
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... SPD Codes for PC2–3200R (–5) Product Type Organization Label Code Jedec SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used 8 ...
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Product Type Organization Label Code Jedec SPD Revision Byte# Description t 27 [ns] RP.min 28 t [ns] RRD.min t 29 [ns] RCD.min t 30 [ns] RAS.min 31 Module Density per Rank and [ns] AS.min CS.min 33 t ...
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Product Type Organization Label Code Jedec SPD Revision Byte# Description 59 Psi(ca) REG 60 T PLL Toggle Rate REG 62 SPD Revision 63 Checksum of Bytes 0-62 64 JEDEC ID Code of Infineon ( JEDEC ...
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Product Type Organization Label Code Jedec SPD Revision Byte# Description 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) ...
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Package Outline 7.1 Raw Card A Module Package DDR2 Registered DIMM Modules Raw Card A one physical rank, 9 components x8 organised 4.0 pin 1 5,175 pin 121 3 Detail of Contacts A 1.0 note: all outline dimensions and ...
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Raw Card B Module Package DDR2 Registered DIMM Modules Raw Card B two one physical rank, 18 components x8 organised 3,0 5,1 75 pin ...
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Raw Card C Module Package DDR2 Registered DIMM Modules Raw Card C one physical rank, 18 components x4 organised 3,0 5,1 75 pin ...
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Raw Card (tbd) Module Package DDR2 Registered DIMM Modules Raw Card (tbd.) two physical ranks, 36 components x4 organised - planar version 4.0 pin 1 5,175 pin 121 3 Detail of Contacts A 1.0 note: all outline dimensions and ...
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... G 7 Product Variations 8 Package 9 Module Type 10 Speed Grade 11 Die Revision Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes ...
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Data Sheet Preliminary HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 32 Rev. 0.85, 2004-04 ...
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