STK14CA8-N25I ETC [List of Unclassifed Manufacturers], STK14CA8-N25I Datasheet - Page 12

• Manufacturer Part Number: STK14CA8-N25I
• Description: 128K x 8 AutoStoreTM nvSRAM QuantumTrapTM CMOS Nonvolatile Static RAM
• Manufacturer: ETC [List of Unclassifed Manufacturers]

STK14CA8
December 2004
HARDWARE STORE ( HSB )
The STK14CA8 provides the
and acknowledging the STORE operations. The HSB
pin can be used to request a hardware STORE cycle.
When the
conditionally initiate a STORE operation after t
An actual STORE cycle will only begin if a WRITE to
the SRAM took place since the last STORE or
RECALL cycle. The
drain driver that is internally driven low to indicate a
busy condition while the STORE (initiated by any
means) is in progress.
SRAM READ and WRITE operations that are in
progress when
given time to complete before the STORE operation
is initiated. After
continue SRAM operations for t
multiple SRAM READ operations may take place. If
a WRITE is in progress when
will be allowed a time, t
any SRAM WRITE cycles requested after
low will be inhibited until
During any STORE operation, regardless of how it
was initiated, the STK14CA8 will continue to drive
the
is complete. Upon completion of the STORE
operation the STK14CA8 will remain disabled until
the
If
HARDWARE RECALL (POWER-UP)
During power up, or after any low-power condition
(V
latched. When V
voltage
automatically be initiated and will take t
complete.
CC
HSB
HSB
HSB
< V
is not used, it should be left unconnected.
SWITCH
pin low, releasing it only when the STORE
pin returns high.
of
HSB
), an internal RECALL request will be
V
pin is driven low, the STK14CA8 will
HSB
SWITCH
CC
HSB
once again exceeds the sense
is driven low by any means are
HSB
,
goes low, the STK14CA8 will
DELAY
HSB
a
pin also acts as an open
, to complete. However,
RECALL
returns high.
HSB
DELAY
HSB
OPERATION
pin for controlling
. During t
is pulled low it
cycle
HRECALL
HSB
DELAY
goes
DELAY
will
12
to
,
.
SOFTWARE STORE
Data can be transferred from the SRAM to the
nonvolatile memory by a software address sequence.
The STK14CA8 software STORE cycle is initiated by
executing sequential
six specific address locations in exact order. During
the STORE cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the
nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the
cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is important
that no other READ or WRITE accesses intervene in
the sequence, or the sequence will be aborted and no
STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
The software sequence may be clocked with
controlled READs or
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that
sequence to be valid. After the t
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile memory
to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence of
READ operations in a manner similar to the software
STORE initiation. To initiate the RECALL cycle, the
following sequence of
must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6.
Read address
Document Control #ML0022 rev 1.0
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
G
E
E
controlled READs.
controlled READ cycles from
controlled READ operations
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
STORE
G
be low for the
cycle time has
E