M59DR032A100N1T STMICROELECTRONICS [STMicroelectronics], M59DR032A100N1T Datasheet - Page 8

• Manufacturer Part Number: M59DR032A100N1T
• Description: 32 Mbit 2Mb x16, Dual Bank, Page Low Voltage Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M59DR032A, M59DR032B
INSTRUCTIONS AND COMMANDS
Seventeen instructions are defined (see Table
14A), and the internal P/E.C. automatically han-
dles all timing and verification of the Program and
Erase operations. The Status Register Data Poll-
ing, Toggle, Error bits can be read at any time, dur-
ing programming or erase, to monitor the progress
of the operation.
Instructions, made up of one or more commands
written in cycles, can be given to the Program/
Erase Controller through a Command Interface
(C.I.). The C.I. latches commands written to the
memory. Commands are made of address and
data sequences. Two Coded Cycles unlock the
Command Interface. They are followed by an input
command or a confirmation command. The Coded
Sequence consists of writing the data AAh at the
address 555h during the first cycle and the data
55h at the address 2AAh during the second cycle.
Instructions are composed of up to six cycles. The
first two cycles input a Coded Sequence to the
Command Interface which is common to all in-
structions (see Table 14A). The third cycle inputs
the instruction set-up command. Subsequent cy-
cles output the addressed data, Electronic Signa-
ture, Block Protection, Configuration Register
Status or CFI Query for Read operations. In order
to give additional data protection, the instructions
for Block Erase and Bank Erase require further
command inputs. For a Program instruction, the
fourth command cycle inputs the address and data
to be programmed. For a Double Word Program-
ming instruction, the fourth and fifth command cy-
cles
programmed. For a Block Erase and Bank Erase
instructions, the fourth and fifth cycles input a fur-
ther Coded Sequence before the Erase confirm
command on the sixth cycle. Any combination of
blocks of the same memory bank can be erased.
Erasure of a memory block may be suspended, in
order to read data from another block or to pro-
gram data in another block, and then resumed.
When power is first applied the command interface
is reset to Read Array.
Command sequencing must be followed exactly.
Any invalid combination of commands will reset
the device to Read Array. The increased number
of cycles has been chosen to ensure maximum
data security.
8/38
input
the
address
and
data
to
be
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded Cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read.
CFI Query (RCFI) Instruction. Common
Interface Query mode is entered writing 98h at ad-
dress 55h. The CFI data structure gives informa-
tion on the device, such as the sectorization, the
command set and some electrical specifications.
Tables 15, 16, 17 and 18 show the addresses
used to retrieve each data. The CFI data structure
contains also a security area; in this section, a 64
bit unique security number is written, starting at
address 80h. This area can be accessed only in
read mode by the final user and there are no ways
of changing the code after it has been written by
ST. Write a read instruction (RD) to return to Read
mode.
Table 12. Commands
Hex Code
00h
10h
20h
30h
40h
60h
80h
90h
98h
A0h
B0h
F0h
Bypass Reset
Bank Erase Confirm
Unlock Bypass
Block Erase Resume/Confirm
Double Word Program
Block Protect, or
Block Unprotect, or
Block Lock, or
Write Configuration Register
Set-up Erase
Read Electronic Signature, or
Block Protection Status, or
Configuration Register Status
CFI Query
Program
Erase Suspend
Read Array/Reset
Command
Flash