AT17F16-30CC ATMEL [ATMEL Corporation], AT17F16-30CC Datasheet - Page 5

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AT17F16-30CC

Manufacturer Part Number
AT17F16-30CC
Description
FPGA Configuration Flash Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
DATA
CLK
PAGE_EN
3392A–CNFG–10/03
(1)
(1)
(2)
Pin Description
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
Input used to enable page download mode. When PAGE_EN is high the configuration
download address space is partitioned into 4 equal pages. This gives users the ability to
easily store and retrieve multiple configuration bitstreams from a single configuration
device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be
remain low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no
effect.
Notes:
Name
DATA
CLK
PAGE_EN
PAGESEL0
PAGESEL1
RESET/OE
CE
GND
CEO
A2
READY
SER_EN
V
CC
1. This pin has an internal 20 K
2. This pin has an internal 30 K
I/O
I/O
O
O
I
I
I
I
I
I
I
I
LAP
8
1
2
3
4
5
6
7
8
pull-up resistor.
pull-down resistor.
PLCC
20
16
10
14
15
17
20
11
2
4
7
6
8
AT17F16
PLCC
44
20
25
19
21
24
27
29
41
44
2
5
1
TQFP
44
40
43
39
14
19
13
15
18
21
23
35
38
5

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