PSD4235G2-12UIT STMICROELECTRONICS [STMicroelectronics], PSD4235G2-12UIT Datasheet - Page 48

• Manufacturer Part Number: PSD4235G2-12UIT
• Description: Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Memory Select signals
12.3
12.4
48/124
register by using PSDsoft Express to configure it for Boot-up and having the MCU change it
when desired.
Table 24
Figure 7.
Separate space modes
Program space is separated from Data space. For example, Program Select Enable (PSEN,
CNTL2) is used to access the program code from the primary Flash memory, while Read
Strobe (RD, CNTL1) is used to access data from the secondary Flash memory, SRAM and
I/O Port blocks. This configuration requires the VM register to be set to 0Ch (see
Combined space modes
The Program and Data spaces are combined into one memory space that allows the
primary Flash memory, secondary Flash memory, and SRAM to be accessed by either
Program Select Enable (PSEN, CNTL2) or Read Strobe (RD, CNTL1). For example, to
configure the primary Flash memory in Combined space, bits 2 and 4 of the VM register are
set to ’1’ (see
describes the VM register.
Priority level of memory and I/O components
Figure
9).
Highest Priority
Lowest Priority
Primary Flash Memory
Non-Volatile Memory
SRAM, I/O, or
Peripheral I/O
Secondary
Level 1
Level 2
Level 3
AI02867D
PSD4235G2V
Figure
8).