PSD4235G2-12UIT STMICROELECTRONICS [STMicroelectronics], PSD4235G2-12UIT Datasheet - Page 55

• Manufacturer Part Number: PSD4235G2-12UIT
• Description: Flash in-system programmable (ISP) peripherals for 16-bit MCUs (3.3 V supply)
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

RT A,B,F)
AD/WRITE CONTROL SIGNALS)
KIN,CSI)
UT)
PSD4235G2V
16
Figure 12. DPLD logic array
0] (FEEDBACKS)
0] (FEEDBACKS)
1. The address inputs are A19-A4 when in 80C51XA mode
2. Additional address lines can be brought into the PSD via Port A, B, C, D, or F.
Decode PLD (DPLD)
The DPLD, shown in
components. The DPLD can be used to generate the following decode signals:
●
●
●
●
●
●
8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms
each)
4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three
product terms each)
1 internal SRAM Select (RS0) signal (three product terms)
1 internal CSIOP Select (PSD Configuration register) signal
1 JTAG Select signal (enables JTAG-ISP on Port E)
2 internal Peripheral Select signals
(Peripheral I/O mode).
(INPUTS)
(32)
(16)
(8)
(8)
(8)
(4)
(1)
(3)
(1)
(1)
Figure
12, is used for decoding the address for internal and external
3
3
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
RS0
CSIOP
PSEL0
PSEL1
JTAGSEL
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS1
FS7
FS2
FS3
FS5
FS6
FS4
SRAM SELECT
PERIPHERAL I/O MODE
SELECT
I/O DECODER
SELECT
8 PRIMARY FLASH
MEMORY SECTOR SELECTS
Decode PLD (DPLD)
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