NCP1336 ONSEMI [ON Semiconductor], NCP1336 Datasheet - Page 11

• Manufacturer Part Number: NCP1336
• Description: Quasi-Resonant Current Mode Controller for High Power Universal Off-Line Supplies
• Manufacturer: ONSEMI [ON Semiconductor]

= It which implies a 22 mF x 0.9 V / 150 mA = 132 ms startup
time for the first sequence. The second sequence is obtained
by changing I to 3 mA (worst case calculation) with DV =
15 V − 0.9 V = 14.1 V, which finally leads to a second startup
time of 22 mF x 14.1 V / 3 mA = 103 ms. The total startup
time becomes 103 ms + 132 ms = 235 ms. Please note that
this calculation is approximated by the presence of the knee
in the vicinity of the transition.
on pin 9 and the auxiliary winding increases the voltage on
the V
NCP1336 Operation
the auxiliary winding of the transformer. The typical
detection level is fixed at 55 mV. When a valley is detected,
the decimal counter is incremented. The operating valley
(1
voltage decreases or increases, the valley comparators
st
The first startup period is calculated by the formula, CV
As soon as V
The valley detection is done by monitoring the voltage of
, 2
CC
nd
, 3
pin. At the same time, the controller smoothly
rd
or 4
Figure 5. An error flag gets asserted as soon as the current setpoint reaches its upper limit
CC
th
(0.8 V/R
reaches VCC
) is determined by the FB voltage. As FB
sense
). Here the timer lasts 50 ms, a 100 nF capacitor being connected to pin 3.
on
, drive pulses are delivered
http://onsemi.com
11
ramps up the peak current to I
reached after a typical 5 ms soft−start period. As soon as the
CS voltage reaches 0.8 V = I
IpFlag is asserted. When the error flag is asserted, the current
source on pin 3 is activated and charges up the capacitor
connected to this pin. If the error flag is still asserted when
the timer capacitor has reached the threshold level
VtimFault, then the controller assumes that the power
supply has really undergone a fault condition and
immediately stops all pulses to enter a safe burst operation.
Figure 5 depicts the V
sequence, showing the state of the error flag:
toggle one after another to select the proper valley. The
activation of an “n” valley comparator disables the “n+1” or
“n−1” valley comparator (depending if FB increases or
decreases) and enables the corresponding “n” output of the
decimal counter. Figure 6 shows the internal arrangement of
the valley selection circuitry.
CC
evolution during a proper startup
Limit1
max
(0.8 V / R
, the internal error flag
sense
) which is