NCP1381 ONSEMI [ON Semiconductor], NCP1381 Datasheet - Page 9

• Manufacturer Part Number: NCP1381
• Description: Low−Standby High Performance PWM Controller
• Manufacturer: ONSEMI [ON Semiconductor]

Quasi−Resonance Operation
permanently monitors the transformer core flux activity and
ensures Borderline Conduction Mode (BCM) operation.
That is to say, when the switch closes, the current ramps up
in the magnetizing inductance L
imposed by the feedback loop. At this point, the power
switch opens and the energy transfers from the primary side
to the secondary (isolated) portion. The secondary diode is
now biased and the output voltage “flies back” to the
primary side, now demagnetizing the primary inductance
L
said to be “reset” (ö = 0). At this time, we can turn the
MOSFET on again to create a new cycle. Figure 7 and 8
portray the typical waveforms with their associated
captions. If a delay TW is introduced further to the core reset
detection and before biasing the power MOSFET, the drain
signal Vds(t) has the time to go through a minimum, also
called valley. Therefore, when we will finally reactivate the
power MOSFET, its drain−to−source voltage will be
minimum, reducing capacitive losses but also its
gate−charge value, since the Miller effect gets diminished at
low Vds.
DRV
V
Bunch Length Given by Timer
If V
counts, pulses are immediately stopped and the latchoff phase
is entered. Here, in this example, the timer was set to 100 ms.
P
CC
Quasi−Resonance (QR) implies that the controller
. When this current reaches zero, the transformer core is
CC
drops below VCC
100 ms
OFF
Figure 6.
during a portion where the timer
P
Bunch Length Given
by VCC
until it reaches a setpoint
< 100 ms
OFF
VCC
VCC
OFF
ON
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NCP1381
9
The flux activity monitoring is actually made via an
auxiliary winding, obeying the law, V
Figure 9 describes how the detection is made, since the
signal obtained on the auxiliary winding is centered to zero.
Let’s split the events with their associated circuitry:
t
and current grows−up in the primary winding. This is the on
portion of Figure 8, left side of the triangle. When the driver
output went high, its rising edge triggered a 8 ms timer. This
8 ms timer provides a true frequency clamp by driving the
D−input of the flip−flop. Now, when the peak current
reaches the level imposed by the feedback loop, a reset
occurs and the flip−flop output comes low.
(DRV
are stopped and the controller enters a safe, autorecovery,
restart mode. This condition can occur if the current sense
pin does not receive any signal from the sense resistor or if
a short−circuit brings the CS pin to ground for instance.
ON
The D flip−flop output is high, the MOSFET is enhanced
If for any reason the controller keeps the gate high
Figure 7. Typical Quasi−Resonance Waveform
out
s
Figure 8. Magnetizing Inductance Current
ON
) implying a t
t
ON
+
V
L
in
P
ON
Leakage
ON
Ringing
I
peak
Waveforms
longer than 50 ms, then all pulses
0
1st Valley
OFF
s
OFF
t
OFF
TW
+ N @
I
P
= 0
aux
(V
TW
out
= N . dö / dt.
L
) V
P
f
)