LT3071EUFD LINER [Linear Technology], LT3071EUFD Datasheet - Page 11

• Manufacturer Part Number: LT3071EUFD
• Description: 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining
• Manufacturer: LINER [Linear Technology]

pin Functions
VIOC (Pin 1): Voltage for In-to-Out Control. The IC in-
corporates a unique tracking function to control a buck
regulator powering the LT3071’s input. The VIOC pin is
the output of this tracking function that drives the buck
regulator to maintain the LT3071’s input voltage at V
300mV. This function maximizes efficiency and minimizes
power dissipation. See the Applications Information sec-
tion for more information on proper control of the buck
regulator.
PWRGD (Pin 2): Power Good. The PWRGD pin is an open-
drain NMOS output that actively pulls low if any one of
these fault modes is detected:
• V
• V
• Junction temperature typically exceeds 145°C.
• V
• The OUT-to-IN reverse-current detector activates.
See the Applications Information section for more infor-
mation on PWRGD fault modes.
REF/BYP (Pin 3): Reference Filter. The pin is the output
of the bandgap reference and has an impedance of ap-
proximately 19kΩ. This pin must not be externally loaded.
Bypassing the REF/BYP pin to GND with a 10nF capacitor
decreases output voltage noise and provides a soft-start
function to the reference. LTC recommends the use of a
high quality, low leakage capacitor. See the Applications
Information section for more information on noise and
output voltage margining considerations.
edge of V
25µs.
OUT
OUT
BIAS
is less than 90% of V
drops below 85% of V
is less than its undervoltage lockout threshold.
OUT
.
OUT(NOMINAL)
OUT(NOMINAL)
for more than
on the rising
OUT
+
GND (Pins 4, 9-14, 20, 26, Exposed Pad Pin 29): Ground.
The exposed pad of the QFN package is an electrical con-
nection to GND. To ensure proper electrical and thermal
performance, solder Pin 29 to the PCB ground and tie to
all GND pins of the package. These GND pins are fused
to the internal die attach paddle and the exposed pad to
optimize heat sinking and thermal resistance characteris-
tics. See the Applications Information section for thermal
considerations and calculating junction temperature.
IN (Pins 5, 6, 7, 8): Input Supply. These pins supply
power to the high current pass transistor. Tie all IN pins
together for proper performance. The LT3071 requires a
bypass capacitor at IN to maintain stability and low input
impedance over frequency. A 47µF input bypass capacitor
suffices for most battery and power plane impedances.
Minimizing input trace inductance optimizes performance.
Applications that operate with low V
voltages and that have large, fast load transients may require
much higher input capacitor requirements to prevent the
input supply from drooping and allowing the regulator to
enter dropout. See the Applications Information section
for more information on input capacitor requirements.
OUT (Pins 15, 16, 17, 18): Output. These pins supply
power to the load. Tie all OUT pins together for proper
performance. A minimum output capacitance of 15µF is
required for stability. LTC recommends low ESR, X5R or
X7R dielectric ceramic capacitors for best performance.
A parallel ceramic capacitor combination of 10µF + 4.7µF
+ 2.2µF or 15 1µF ceramic capacitors in parallel provide
excellent stability and load transient response. Large load
transient applications require larger output capacitors to
limit peak voltage transients. See the Applications Infor-
mation section for more information on output capacitor
requirements.
IN
-V
OUT
LT3071
differential

3071f