LT3071EUFD LINER [Linear Technology], LT3071EUFD Datasheet - Page 15

• Manufacturer Part Number: LT3071EUFD
• Description: 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator with Analog Margining
• Manufacturer: LINER [Linear Technology]

ApplicAtions inFormAtion
FPGA and ASIC processors are sufficient to stabilize the
system (see Stability and Output Capacitance section). This
regulator design provides ample bandwidth and responds
to transient load changes in a few hundred nanoseconds
versus regulators that respond in many microseconds.
The LT3071 also incorporates precision current limiting,
enable/disable control of output voltage and integrated
overvoltage and thermal shutdown protection. The
LT3071’s unique design combines the benefits of low
dropout voltage, high functional integration, precision
performance and UltraFast transient response, as well as
providing significant cost savings on the output capacitance
needed in fast load transient applications.
As lower voltage applications become increasingly preva-
lent with higher frequency switching power supplies, the
LT3071 offers superior regulation and an appreciable
component cost savings. The LT3071 steps to the next
level of performance for the latest generation FPGAs, DSPs
and microprocessors. The simple versatility and benefits
derived from these circuits exceed the power supply needs
of today’s high performance microprocessors.
Programming Output Voltage
Three tri-level input pins, V
value of output voltage. Table 1 illustrates the 3-bit digital
word to output voltage resulting from setting these pins
high, low or allowing them to float.
These pins may be tied high or low by either pin-strapping
them to V
float may either actually float or require logic that has
Hi-Z output capability. This allows output voltage to be
dynamically changed if necessary.
Output voltage is selectable from a minimum of 0.8V to
a maximum of 1.8V in increments of 50mV. The MSB,
V
V
O2
O0
, sets the pedestal voltage, and the LSB’s, V
increment V
BIAS
or driving them with digital ports. Pins that
OUT
.
O2
, V
O1
and V
O0
, select the
O1
and
Output voltage is limited to 1.8V maximum by an internal
override of V
Table 1: V
X = Don’t Care, 0 = Low, Z = Float, 1 = High
The input logic low threshold is less than 250mV refer-
enced to GND and the logic high threshold is greater than
V
as set by a window comparator defines the logic Hi-Z
state.
REF/BYP—Voltage Reference
This pin is the buffered output of the internal bandgap
reference and has an output impedance of ≅19kΩ. The
design includes an internal compensation pole at f
A 10nF REF/BYP capacitor to GND creates a lowpass pole
at f
voltage noise to about 10µV
ence. The LT3071 only soft-starts the reference voltage
during an initial turn-on sequence. If the EN pin is toggled
low after initial turn-on, the reference remains powered-up.
Therefore, toggling the EN pin from low to high does not
soft-start the reference. Only by turning the BIAS supply
voltage on and off will the reference be soft-started. Output
voltage noise is the RMS sum of the reference voltage
noise in addition to the amplifier noise.
V
BIAS
0
0
0
0
0
0
0
0
0
Z
Z
O2
LP
= 840Hz. The 10nF capacitor decreases reference
– 250mV. The range between these two thresholds
V
0
0
0
Z
Z
Z
1
1
1
0
0
O1
O2
to V
V
O1
0
Z
1
0
Z
1
0
Z
1
0
Z
O0
O0
(default to low) when V
Settings vs Output Voltage
V
OUT(NOM)
0.80V
0.85V
0.90V
0.95V
1.00V
1.05V
1.10V
1.15V
1.20V
1.25V
1.30V
RMS
V
Z
Z
Z
Z
Z
Z
Z
1
1
1
O2
and soft-starts the refer-
V
0
Z
Z
Z
1
1
1
X
X
X
O1
O2
V
1
0
Z
1
0
Z
1
0
Z
1
= high.
O0
LT3071
V
OUT(NOM)
C
1.35V
1.40V
1.45V
1.50V
1.55V
1.60V
1.65V
1.70V
1.75V
1.80V
= 4kHz.

3071f