NCP5201_06 ONSEMI [ON Semiconductor], NCP5201_06 Datasheet
NCP5201_06
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NCP5201_06 Summary of contents
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NCP5201 Dual Output DDR Power Controller The NCP5201 Dual DDR Power Controller is specifically designed as a total power solution for a high current DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply ...
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VSTBY 1.15 k C10 100 nF C11 R12 6 R10 1.1 k C13 22 nF C17 0.1 mF AGND MAXIMUM RATINGS Rating Power Supply Voltage (Pin ...
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ELECTRICAL CHARACTERISTICS (VSTBY = 5.0 V, VCC = RL1 = 100 kW 1.0 kW, R10 = 1.0 k, R12 = 20 kW C12 = 3.0 nF, C11 = 6.0 nF, C10 ...
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ELECTRICAL CHARACTERISTICS RL1 = 100 kW 1.0 kW, R10 = 1.0 k, R12 = 20 kW C12 = 3.0 nF, C11 = 6.0 nF, C10 = 80 nF, for min/max values unless otherwise noted) ...
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Voltage and Current Reference S3_EN 12 V VCC 12 V− UVLO + − VREF VSTBY 5 VST− VSTBY UVLO + VSTGD − VREF PWRGD S0 OSC PGND S3 SS SC2PWR + R − SC2GND + R − GND ...
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DETAILED OPERATION DESCRIPTIONS General The NCP5201 Dual DDR Power Controller combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of a linear regulator for the VTT memory termination voltage. VTT is designed to automatically track ...
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VDDQ Regulator in Standby Mode (S3) An internal P−Channel power FET switching at 500 kHz (doubled frequency), with peak current limit preset at 2.0 A, provides nonsynchronous switch−mode control while in the S3 state. In this mode, the internal P−Channel ...
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VSTBY S3_EN VCC VDDQ tss1 Soft−Start VTT ∼ 200 ms t hold PWRGD Operating Mode S5 VSTGD goes HIGH INREGVTT goes HIGH INREGDDQ goes HIGH, VTT is activated 12 VGD goes HIGH, VDDQ is activated Figure 3. Power−Up and Power−Down ...
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D PIN 1 LOCATION 2X 0. 0.15 C TOP VIEW 0.10 C 18X 0.08 C SIDE VIEW 18X 1 K 18X 18 18X BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, ...