NCP5422A_06 ONSEMI [ON Semiconductor], NCP5422A_06 Datasheet - Page 15

• Manufacturer Part Number: NCP5422A_06
• Description: Dual Out−of−Phase Synchronous Buck Controller with Current Limit
• Manufacturer: ONSEMI [ON Semiconductor]

board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.
circuit board, the following checklist should be used to
ensure proper operation of the NCP5422A.
When laying out the CPU buck regulator on a printed
1. Rapid changes in voltage across parasitic capacitors
2. Keep high currents out of sensitive ground
3. Avoid ground loops as they pick up noise. Use star or
4. For high power buck regulators on double−sided
5. Even though double sided PCB’s are usually
and abrupt changes in current in parasitic inductors
are major concerns for a good layout.
connections.
single point grounding.
PCB’s a single ground plane (usually the bottom) is
recommended.
sufficient for a good layout, four−layer PCB’s are the
optimum approach to reducing susceptibility to
noise. Use the two internal layers as the power and
GND planes, the top layer for power connections and
component vias, and the bottom layers for the noise
sensitive traces.
LAYOUT GUIDELINES
NCP5422A, NCP5423
http://onsemi.com
15
10. Place the output capacitors as close to the load as
11. Place the COMP capacitor as close as possible to the
12. Connect the filter components of the following pins:
13. Place the V
14. Place the R
15. Include provisions for 100−100pF capacitor across
16. Assign the output with lower duty cycle to channel 2,
6. Keep the inductor switching node small by placing
7. The MOSFET gate traces to the IC must be short,
8. Use fewer, but larger output capacitors, keep the
9. Place the switching MOSFET as close to the input
the output inductor, switching and synchronous FETs
close together.
straight, and wide as possible.
capacitors clustered, and use multiple layer traces
with heavy copper to keep the parasitic resistance
low.
capacitors as possible.
possible.
COMP pin.
R
single trace, and connect this local GND trace to the
output capacitor GND.
to the IC.
R
each resistor of the feedback network to improve
noise immunity and add COMP.
which has better noise immunity.
OSC,
OSC
pin.
V
FB
, V
CC
OSC
OUT
bypass capacitors as close as possible
resistor as close as possible to the
, and COMP to the GND pin with a