X9525 INTERSIL [Intersil Corporation], X9525 Datasheet

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X9525

Manufacturer Part Number
X9525
Description
Fiber Channel/Gigabit Etherner Laser Diode Control for Fiber Optic Modules
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
Dual DCP, EEPROM Memory
FEATURES
• Two Digitally Controlled Potentiometers (DCP’s)
• 2kbit EEPROM Memory with Write Protect & Block
• Device ID Addressability
• 2-Wire industry standard Serial Interface
• Single Supply Operation
• Hot Pluggable
• Packages
BLOCK DIAGRAM
—100 Tap - 10kΩ
—256 Tap - 50kΩ
—Non-Volatile
—Write Protect Function
Lock
—Complies to the Gigabit Interface Converter
—Adressable
—2.7V to 5.5V
—CSP (Chip Scale Package)
—20 Pin TSSOP
(GBIC) specification
PRELIMINARY
TM
SDA
SCL
WP
A o
RESET LOGIC
THRESHOLD
COMMAND
DECODE &
REGISTER
CONTROL
LOGIC
®
DATA
1
Data Sheet
Fiber Channel/Gigabit Ethernet Laser Diode Control for Fiber Optic Modules
8
4
1-888-INTERSIL or 1-888-352-6832
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
PROTECT
REGISTER
CONSTAT
EEPROM
LOGIC
ARRAY
2kbit
©2001 Intersil Inc., Patents Pending. Copyright Intersil Americas Inc. 2005. All Rights Reserved
DESCRIPTION
The X9525 combines two Digitally Controlled Potentiom-
eters (DCP’s), and integrated EEPROM with Block
Lock™ protection. All functions of the X9525 are
accessed by an industry standard 2-Wire serial interface.
The DCP’s of the X9525 may be utilized to control the
bias and modulation currents of the laser diode in a Fiber
Optic module. The 2kbit integrated EEPROM may be
used to store module definition data.
The features of the X9525 are ideally suited to simplifying
the design of fiber optic modules which comply to the Gi-
gabit Interface Converter (GBIC) specification. The inte-
gration of these functions into one package significantly
reduces board area, cost and increases reliability of laser
diode modules.
March 10, 2005
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
NONVOLATILE
NONVOLATILE
REGISTER
REGISTER
COUNTER
COUNTER
MEMORY
MEMORY
WIPER
WIPER
8 - BIT
8 - BIT
R
R
R
R
R
R
H2
W2
L2
H1
W1
L1
X9525
FN8210.0

Related parts for X9525

X9525 Summary of contents

Page 1

... EEPROM with Block Lock™ protection. All functions of the X9525 are accessed by an industry standard 2-Wire serial interface. The DCP’s of the X9525 may be utilized to control the bias and modulation currents of the laser diode in a Fiber Optic module. The 2kbit integrated EEPROM may be used to store module definition data ...

Page 2

... Physical Device Address input. A match in the slave address serial data stream, and the Physical Device Address input pin must be in order to initiate communication with the X9525 maximum of two (2) devices may occupy the same 2-wire serial bus. Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Pro- tection is enabled. In the enabled state, this pin prevents all nonvolatile “ ...

Page 3

... Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions. See Figure 1. On power-up of the X9525, the SDA pin is in the input mode. Serial Start Condition ...

Page 4

... Byte proto- col is used. All operations however must begin with the Slave Address Byte being issued on the SDA pin. The Slave address selects the part of the X9525 to be addressed, and specifies if a Read or Write opera- tion performed. ...

Page 5

... These switches are controlled by the Wiper Counter Register (WCR) (See Figure 6). The WCR is a volatile register. On power-up of the X9525, wiper position data is auto- NO matically loaded into the WCR from its associated Non Issue STOP Volatile Memory (NVM) Register. The intial values of the DCP WCR’ ...

Page 6

... WCR and NVM. Therefore, the new “wiper position” set- ting is recalled into the WCR after Vcc of the X9525 has been powered down then powered back “0” then a DCP Volatile Write is performed. This operation changes the DCP “ ...

Page 7

... The Slave Address Byte 1010A 0 Write to a DCP conducted. An ACKNOWLEDGE is returned by the X9525 after the Slave Address has been received correctly. Next, an Instruction Byte is issued on SDA. Bits P1 and P0 of the Instruction Byte determine which WCR is to ...

Page 8

... Signals from the Slave It should be noted that all writes to any DCP of the X9525 are random in nature. Therefore, the Data Byte of con- secutive write operations to any DCP can differ by an arbitrary number of bits. Also, setting the bits ( ( are reserved sequences, and will result in no ACKNOWLEDGE after sending an Instruction Byte on SDA ...

Page 9

... CONSTAT Register must first be set (See “BL1, BL0: Block Lock protection bits - (Nonvolatile)” on page 12.) The X9525 is capable of a page write operation initi- ated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes ...

Page 10

... ACKNOWLEDGE signal. If the master issues a STOP within a Data Byte, or before the X9525 issues a corresponding ACKNOWLEDGE, the X9525 cancels the write operation. Therefore, the contents of the EEPROM array does not change. EEPROM Array Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one ...

Page 11

... Byte, the master immediately issues another START condition and the Slave Address Byte with the R/W bit set to one. This is followed by an ACKNOWLEDGE from the X9525 and then by the eight bit word. The master ter- minates the read operation by not responding with an ACKNOWLEDGE and instead issuing a STOP condition (Refer to Figure 15.). A similar operation called “ ...

Page 12

... RWEL WEL reset to “0” (by writing 00000000 to the CONSTAT regis- ter) or until the X9525 powers down, and then up again. Writes to the WEL bit do not cause an internal high volt- age write cycle. Therefore, the device is ready for another operation immediately after a STOP condition is executed in the CONSTAT Write command sequence (See Figure 18) ...

Page 13

... The factory default setting for these bits are BL1 = 0, BL0 = 0. IMPORTANT NOTE: If the Write Protect (WP) pin of the X9525 is active (HIGH), then all nonvolatile write opera- tions to both the EEPROM memory and DCPs are inhib- ited, irrespective of the Block Lock bit settings (See "WP: Write Protection Pin" ...

Page 14

... RWEL bit. Block Lock protection of the device enables the user to inhibit writes to certain regions of the EEPROM memory, as well as to all the DCPs. One further level of data protection in the X9525, is incorpo- rated in the form of the Write Protection pin. WP: Write Protection Pin ...

Page 15

... Exposure to absolute maximum rating conditions for extended peri- ods may affect device reliability Figure 20. Equivalent A.C. Circuit Figure 21. DCP SPICE Macromodel 15 X9525 Parameter ( Referenced to Vss ...

Page 16

... F SCL t SU:DAT t SU:STA t HD:STA SDA IN SDA OUT Figure 23. Physical Device Address ( Pin Timing START SCL SDA Figure 24. Write Cycle Timing SCL 8th bit of last byte SDA 16 X9525 HIGH LOW R t HD:DAT Clk 1 t SU:A 0 ACK Stop Condition t SU:STO ...

Page 17

... SDA WP Figure 27. DCP “Wiper Position” Timing Rwx ( x =1,2) R wx( tap position SCL SDA SLAVE ADDRESS BYTE T 17 X9525 Slave Address Clk 1 t SU:WP Address Byte Data INSTRUCTION BYTE Clk 9 t HD:WP ...

Page 18

... V = GND CC. µ with all other µA analog inputs floating ( GND to V OUT µA 10 X9525 is in Standby 0 +0 2.0mA 0.4 V SINK after a STOP ending a write operation. WC after a STOP that initiates WC CC. (1) FN8210.0 March 10, 2005 ...

Page 19

... STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Notes: 1. This parameter is not 100% tested. 19 X9525 Parameter Parameter = 5V) CC ...

Page 20

... Notes: 1. Relative Linearity is a measure of the error in step size between taps = R Notes Minimum Increment = R TOT Notes: 1. Typical values are for T = 25°C and nominal supply voltage. A Notes: 1. This parameter is periodically sampled and not 100% tested. 20 X9525 Limits Min. Typ. -20 Vss Vss 200 ...

Page 21

... X9525 Data Byte Binary 0000 0000 0000 0001 . . 0001 0111 0001 1000 0011 1000 0011 0111 . . 0010 0001 0010 0000 0100 0000 0100 0001 . . 0101 0111 0101 1000 0111 1000 0111 0111 . . 0110 0001 0110 0000 FN8210 ...

Page 22

... X9525 wcr_val = 56; offset = tap_pos - 25; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); wcr_val = 64; offset = tap_pos - 50; for (i=0; i<= offset; i++) wcr_val++ ; return ((unsigned)--wcr_val); wcr_val = 120; offset = tap_pos - 75; for (i=0; i<= offset; i++) wcr_val-- ; return ((unsigned)++wcr_val); FN8210.0 March 10, 2005 ...

Page 23

... Tap DCP encoding formula */ if (tap_pos > 74) return ((unsigned) (195 - tap_pos)); else if (tap_pos > 49) return ((unsigned) (14 + tap_pos)); else if (tap_pos > 24) return ((unsigned) (81 - tap_pos)); else return (tap_pos X9525 /* set to min val */ /* set to max val */ FN8210.0 March 10, 2005 ...

Page 24

... Package Width a Package Length b Package Height c Body Thickness d Ball Height e Ball Diameter f Ball Pitch – Width j Ball Pitch – Length k Ball to Edge Spacing – Width l Ball to Edge Spacing – Length m 24 X9525 ...

Page 25

... PLASTIC, TSSOP PACKAGE TYPE V .025 (.65) BSC .252 (6.4) .300 (6.6) .0075 (.19) .0118 (.30) 0° ° .019 (.50) .029 (.75) Detail A (20X) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) 25 X9525 .169 (4.3) .252 (6.4) BSC .177 (4.5) .047 (1.20) .002 (.05) .006 (.15) .010 (.25) Gage Plane Seating Plane (1.78) (0.42) .031 (.80) ...

Page 26

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 26 X9525 X9525 P T Temperature Range I = Industrial = -40°C to +85°C ...

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