LT3581 LINER [Linear Technology], LT3581 Datasheet - Page 23

• Manufacturer Part Number: LT3581
• Description: 3.3A Boost/Inverting DC/DC Converter with Fault Protection
• Manufacturer: LINER [Linear Technology]

appenDix
Minimum Inductance
Although there can be a tradeoff with efficiency, it is often
desirable to minimize board space by choosing smaller
inductors. When choosing an inductor, there are three
conditions that limit the minimum inductance: (1) provid-
ing adequate load current, (2) avoidance of subharmonic
oscillations and (3) supplying a minimum ripple current
to avoid false tripping of the current comparator.
Adequate Load Current
Small value inductors result in increased ripple currents and
thus, due to the limited peak switch current, decrease the
average current that can be provided to the load. In order
to provide adequate load current, L should be at least:
where:
L
L
BOOST
DUAL
L
L
L
DC
I
η
f
I
PK
OSC
OUT
BOOST
DUAL
DUAL
>
>
2
•
2
f
= L
= L
= L
= Switch Duty Cycle (see Power Switch Duty
= Maximum Peak Switch Current; should not
= Power Conversion Efficiency (typically 88%
= Switching Frequency
= Maximum Output Current
OSC
•
Topologies (see Figures 6 and 7)
Topologies (see Figures 6 and 7)
Cycle section in Appendix)
exceed 3.3A for a combined SW1 + SW2
current, or 1.9A of SW1 current if SW1 is
being used by itself.
for Boost and 75% for Dual Inductor
Topologies at High Currents)
f
OSC
1
1
1
•
DC
DC
for Boost Topologies (see Figure 5)
= L
|| L

 
•
I I
PK
•
•

 
2
2
I
−
(
(
PK
for Coupled Dual Inductor
for Uncoupled Dual Inductor
or
V
V
|
IN
IN
V
−
OUT
V
−
−
|
IN
V
V
V
|
OUT
CESAT
CESAT
•
•
V
IN
I
η
OUT
|
•
•
)
)
I
η
OU
−
I
T T
OUT

 

 
Boost
Topology
SEPIC
or
Inverting
Topologies
Negative values of L
put load current, I
capability of the LT3581.
Avoiding Sub-Harmonic Oscillations
The LT3581’s internal slope compensation circuit will
prevent sub-harmonic oscillations that can occur when
the duty cycle is greater than 50%, provided that the
inductance exceeds a certain minimum value. In applica-
tions that operate with duty cycles greater than 50%, the
inductance must be at least:
where:
Maximum Inductance
Excessive inductance can reduce ripple current to levels
that are difficult for the current comparator (A4 in the Block
Diagram) to cleanly discriminate, causing duty cycle jitter
and/or poor regulation. The maximum inductance can be
calculated by:
where:
L
L
L
L
L
L
L
L
MIN
MIN
MIN
MAX
MAX
MAX
MIN
MAX
=
=
(
= L
= L
= L
= L
= L
= L
V
V
IN
IN
Topologies (see Figures 6 and 7)
Topologies (see Figures 6 and 7)
Topologies (see Figures 6 and 7)
Topologies (see Figures 6 and 7)
350
1
1
1
1
1
1
2 2
−
−
.
for Boost Topologies (see Figure 5)
= L
|| L
for Boost Topologies (see Figure 5)
= L
|| L
V
V
A f
mA
OUT
CESAT
CESAT
2
2
2
2
•
BOOST
for Coupled Dual Inductor
for Uncoupled Dual Inductor
for Coupled Dual Inductor
for Uncoupled Dual Inductor
, exceeds the switch current limit
OSC
)
•
• −
•
or L
f
(
DC
OSC
(
1
2
DUAL
•
DC
DC
)
indicate that the out-
−
1
)
LT3581

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