EL7585 INTERSIL [Intersil Corporation], EL7585 Datasheet - Page 14

• Manufacturer Part Number: EL7585
• Description: TFT-LCD Power Supply
• Manufacturer: INTERSIL [Intersil Corporation]

detected, the outputs and the input protection will turn off
and the chip will power down.
If no fault is found, C
until the sequence is completed.
During the second ramp, the device checks the status of
V
PG output goes low and enables the input protection PMOS
Q1. Q1 is a controlled FET used to prevent in-rush current into
V
on is controlled by C
off and disconnect the inductor from V
With the input protection FET on, NODE1 (See Typical
Application Diagram) will rise to ~V
enabled so V
diode. Hence, there is a step at V
start-up sequence. If this step is not desirable, an external
PMOS FET can be used to delay the output until the boost is
enabled internally. The delayed output appears at A
For EL7585, V
of the third ramp. The soft-start ramp depends on the value
of the C
is ~2ms.
V
peak, DELB gate goes low to turn on the external PMOS Q4
to generate a delayed V
V
PG, V
Fault Protection
During the startup sequence, prior to BOOST soft-start,
V
device temperature is checked. If either of these are not
within the expected range, the part is disabled until the
power is recycled or EN is toggled.
If C
while if C
occur and the sequence will not complete.
Once the start-up sequence is completed, the chip
continuously monitors C
FBB and PG and checks for faults. During this time, the
voltage on the C
fault is detected, or the EN pin is pulled low.
A fault on C
chip immediately. If a fault on any other output is detected,
C
the upper fault threshold (typically 2.4V), at which point the
chip is disabled until the power is recycled or EN is toggled.
If the fault condition is removed prior to the end of the ramp,
the voltage on the C
REF
BOOST
OFF
ON
REF
DELAY
DELAY
is enabled at the beginning of the sixth ramp. A
OFF
and over temperature. At the peak of the second ramp,
turns on at the start of the fourth peak. At the fifth
is checked to be within ±20% of its final value and the
DLY
will ramp up linearly with a 5µA (typical) current to
before V
DELAY
, DELB and V
is shorted low, then the sequence will not start,
DELAY
capacitor. For C
BOOST
BOOST
DLY
is shorted H, the first down ramp will not
BOOST
, V
o
DLY
rises to V
capacitor remains at 1.15V until either a
CDLY
REF
. When a fault is detected, M1 will turn
and V
ON
BOOST
DLY
capacitor returns to 1.15V.
is enabled internally. Its rate of turn
or temperature will shut down the
continues ramping up and down
are checked at end of this ramp.
, DELB, FBP, FBL, FBN, V
LOGIC
DLY
14
IN
-V
output.
BOOST
of 220nF, the soft-start time
DIODE
IN
soft-start at the beginning
. Initially the boost is not
IN
.
during this part of the
through the output
VDD
VDD
REF
.
,
,
EL7585
Typical fault thresholds for FBP, FBL, FBN and FBB are
included in the tables. PG and DELB fault thresholds are
typically 0.6V.
C
voltage within its normal range. If C
boost regulator will attempt to regulate to 0V. If C
shorted H, the regulator switches to P mode.
If any of the regulated outputs (V
V
circuitry will switch off until the output returns to its expected
value.
If V
prevent damage to the chip. While in current limit, the part
acts like a current source and the regulated output will drop.
If the output drops below the fault threshold, a ramp will be
initiated on C
the chip will be disabled on completion of the ramp.
In some circumstances, (depending on ambient temperature
and thermal design of the board), continuous operation at
current limit may result in the over-temperature threshold
being exceeded, which will cause the part to disable
immediately.
All I/O also have ESD protection, which in many cases will
also provide overvoltage protection, relative to either ground
or V
abs max ratings are exceeded.
Component Selection for Start-Up Sequencing and
Fault Protection
The C
to stabilize the V
22nF to 1µF and should not be more than five times the
capacitor on C
The C
range from 47nF minimum to several microfarads - only
limited by the leakage in the capacitor reaching µA levels.
C
above). Note with 220nF on C
typically 50ms and the use of a larger/smaller value will vary
this time proportionally (e.g. 1µF will give a fault time-out
period of typically 230ms).
Fault Sequencing
The EL7585 has an advanced fault detection system which
protects the IC from both adjacent pin shorts during
operation and shorts on the output supplies.
A high quality layout/design of the PCB, in respect of
grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme - especially
during start-up. The user is directed to the layout guidelines
and component selection sections to avoid problems during
initial evaluation and prototype PCB generation.
LOGIC
INT
DEL
BOOST
DD
has an internal current-limited clamp to keep the
REF
DEL
should be at least 1/5 of the value of C
. However, these will not generally operate unless
) are driven above their target levels the drive
capacitor is typically 220nF and has a usable
capacitor is typically set at 220nF and is required
is excessively loaded, the current limit will
DELAY
DEL
REF
to ensure correct start-up operation.
and, provided that the fault is sustained,
output. The range of C
DEL
BOOST
the fault time-out will be
INT
is shorted low, the
, V
ON
REF
REF
, V
OFF
is from
INT
(See
July 1, 2005
is
or
FN7345.1